| /external/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 895 { ISD::FADD, MVT::v2f64, 2 }, in getReductionCost()
896 { ISD::FADD, MVT::v4f32, 4 }, in getReductionCost()
903 { ISD::FADD, MVT::v4f32, 4 }, in getReductionCost()
904 { ISD::FADD, MVT::v4f64, 5 }, in getReductionCost()
905 { ISD::FADD, MVT::v8f32, 7 }, in getReductionCost()
914 { ISD::FADD, MVT::v2f64, 2 }, in getReductionCost()
915 { ISD::FADD, MVT::v4f32, 4 }, in getReductionCost()
922 { ISD::FADD, MVT::v4f32, 3 }, in getReductionCost()
923 { ISD::FADD, MVT::v4f64, 3 }, in getReductionCost()
924 { ISD::FADD, MVT::v8f32, 4 }, in getReductionCost()
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| D | X86IntrinsicsInfo.h | 245 X86_INTRINSIC_DATA(avx512_mask_add_pd_512, INTR_TYPE_2OP_MASK, ISD::FADD,
247 X86_INTRINSIC_DATA(avx512_mask_add_ps_512, INTR_TYPE_2OP_MASK, ISD::FADD,
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| /external/javassist/src/main/javassist/bytecode/ |
| D | Opcode.java | 87 int FADD = 98; field
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| /external/mockito/cglib-and-asm/src/org/mockito/asm/ |
| D | Opcodes.java | 237 int FADD = 98; // - field
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| D | Frame.java | 1087 case Opcodes.FADD: in execute()
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| /external/valgrind/none/tests/ppc64/ |
| D | round.c | 32 FADD, FSUB, FMUL, FDIV, FMADD, enumerator
940 case FADD: in check_double_guarded_arithmetic_op()
1107 case FADD: in check_double_guarded_arithmetic_op()
1208 for (op = FADD; op <= FSQRT; op++) { in test_float_arithmetic_ops()
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| /external/valgrind/none/tests/ppc32/ |
| D | round.c | 32 FADD, FSUB, FMUL, FDIV, FMADD, enumerator
940 case FADD: in check_double_guarded_arithmetic_op()
1107 case FADD: in check_double_guarded_arithmetic_op()
1208 for (op = FADD; op <= FSQRT; op++) { in test_float_arithmetic_ops()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 3977 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2()
3980 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in getLimitedPrecisionExp2()
3993 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2()
3996 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in getLimitedPrecisionExp2()
3999 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, in getLimitedPrecisionExp2()
4014 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2()
4017 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in getLimitedPrecisionExp2()
4020 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, in getLimitedPrecisionExp2()
4023 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, in getLimitedPrecisionExp2()
4026 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, in getLimitedPrecisionExp2()
[all …]
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| D | DAGCombiner.cpp | 533 case ISD::FADD: in isNegatibleForFree()
594 case ISD::FADD: in GetNegatedExpression()
1348 case ISD::FADD: return visitFADD(N); in visit()
7204 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N1); in visitFADD()
7208 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N0); in visitFADD()
7233 if (N1CFP && N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() && in visitFADD()
7235 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0.getOperand(0), in visitFADD()
7236 DAG.getNode(ISD::FADD, SDLoc(N), VT, in visitFADD()
7257 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT, in visitFADD()
7264 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD && in visitFADD()
[all …]
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| D | LegalizeVectorOps.cpp | 267 case ISD::FADD: in LegalizeOp()
965 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO); in ExpandUINT_TO_FLOAT()
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| D | SelectionDAGDumper.cpp | 186 case ISD::FADD: return "fadd"; in getOperationName()
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| D | LegalizeDAG.cpp | 2497 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub); in ExpandLegalINT_TO_FP()
2516 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt); in ExpandLegalINT_TO_FP()
2553 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2); in ExpandLegalINT_TO_FP()
2601 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); in ExpandLegalINT_TO_FP()
3415 case ISD::FADD: in ExpandNode()
3472 if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) && in ExpandNode()
3475 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1); in ExpandNode()
4207 case ISD::FADD: in PromoteNode()
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| D | LegalizeFloatTypes.cpp | 73 case ISD::FADD: R = SoftenFloatRes_FADD(N); break; in SoftenFloatResult()
889 case ISD::FADD: ExpandFloatRes_FADD(N, Lo, Hi); break; in ExpandFloatResult()
1335 Lo = DAG.getNode(ISD::FADD, dl, VT, Hi, in ExpandFloatRes_XINT_TO_FP()
1752 case ISD::FADD: in PromoteFloatResult()
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| D | SelectionDAGBuilder.h | 727 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); } in visitFAdd()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 232 FADD, FSUB, FMUL, FDIV, FREM, enumerator
|
| /external/mockito/cglib-and-asm/src/org/mockito/asm/tree/analysis/ |
| D | BasicInterpreter.java | 247 case FADD: in binaryOperation()
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| D | BasicVerifier.java | 249 case FADD: in binaryOperation()
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| D | Frame.java | 426 case Opcodes.FADD: in execute()
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 1102 FADD = FPDataProcessing2SourceFixed | 0x00002000, enumerator
1103 FADD_s = FADD,
1104 FADD_d = FADD | FP64,
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.cpp | 363 setOperationAction(ISD::FADD, VT, Expand); in AMDGPUTargetLowering()
396 setTargetDAGCombine(ISD::FADD); in AMDGPUTargetLowering()
1062 return DAG.getNode(ISD::FADD, DL, VT, in LowerIntrinsicLRP()
1602 SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT, in LowerDIVREM24()
1928 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFCEIL()
2004 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); in LowerFRINT()
2048 return DAG.getNode(ISD::FADD, SL, MVT::f32, T, Sel); in LowerFROUND32()
2138 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFFLOOR()
2161 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo); in LowerINT_TO_FP64()
2187 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi); in LowerUINT_TO_FP()
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| D | SIISelLowering.cpp | 210 setTargetDAGCombine(ISD::FADD); in SITargetLowering()
1654 case ISD::FADD: { in PerformDAGCombine()
1674 if (LHS.getOpcode() == ISD::FADD) { in PerformDAGCombine()
1683 if (RHS.getOpcode() == ISD::FADD) { in PerformDAGCombine()
1708 if (LHS.getOpcode() == ISD::FADD) { in PerformDAGCombine()
1720 if (RHS.getOpcode() == ISD::FADD) { in PerformDAGCombine()
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| /external/javassist/src/main/javassist/compiler/ |
| D | CodeGen.java | 934 '+', DADD, FADD, LADD, IADD,
1730 bytecode.addOpcode(token == PLUSPLUS ? FADD : FSUB); in atPlusPlus()
1808 bytecode.addOpcode(token == PLUSPLUS ? FADD : FSUB); in atPlusPlusCore()
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| /external/vixl/src/vixl/a64/ |
| D | constants-a64.h | 1195 FADD = FPDataProcessing2SourceFixed | 0x00002000, enumerator
1196 FADD_s = FADD,
1197 FADD_d = FADD | FP64,
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1422 setOperationAction(ISD::FADD, MVT::f32, Legal); in HexagonTargetLowering()
1423 setOperationAction(ISD::FADD, MVT::f64, Expand); in HexagonTargetLowering()
1513 setOperationAction(ISD::FADD, MVT::f32, Expand); in HexagonTargetLowering()
1514 setOperationAction(ISD::FADD, MVT::f64, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedA57.td | 422 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>;
424 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>;
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