Searched refs:FMINNUM (Results 1 – 17 of 17) sorted by relevance
/external/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 500 FMINNUM, FMAXNUM, enumerator
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D | BasicTTIImpl.h | 587 ISD = ISD::FMINNUM; in getIntrinsicInstrCost()
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D | SelectionDAG.h | 1059 case ISD::FMINNUM:
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/external/llvm/lib/Target/R600/ |
D | SIISelLowering.cpp | 79 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in SITargetLowering() 212 setTargetDAGCombine(ISD::FMINNUM); in SITargetLowering() 1529 case ISD::FMINNUM: in minMaxOpcToMin3Max3Opc() 1618 case ISD::FMINNUM: in PerformDAGCombine()
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D | AMDGPUISelLowering.cpp | 129 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in AMDGPUTargetLowering() 361 setOperationAction(ISD::FMINNUM, VT, Expand); in AMDGPUTargetLowering() 947 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq, in LowerINTRINSIC_WO_CHAIN()
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | SelectionDAGDumper.cpp | 145 case ISD::FMINNUM: return "fminnum"; in getOperationName()
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D | LegalizeFloatTypes.cpp | 71 case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break; in SoftenFloatResult() 887 case ISD::FMINNUM: ExpandFloatRes_FMINNUM(N, Lo, Hi); break; in ExpandFloatResult() 1755 case ISD::FMINNUM: in PromoteFloatResult()
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D | LegalizeVectorOps.cpp | 298 case ISD::FMINNUM: in LegalizeOp()
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D | LegalizeVectorTypes.cpp | 109 case ISD::FMINNUM: in ScalarizeVectorResult() 656 case ISD::FMINNUM: in SplitVectorResult() 1753 case ISD::FMINNUM: in WidenVectorResult()
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D | LegalizeDAG.cpp | 3284 case ISD::FMINNUM: in ExpandNode() 4212 case ISD::FMINNUM: in PromoteNode()
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D | DAGCombiner.cpp | 1366 case ISD::FMINNUM: return visitFMINNUM(N); in visit() 4727 unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM; in combineMinNumMaxNum() 4738 unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM; in combineMinNumMaxNum() 8306 return DAG.getNode(ISD::FMINNUM, SDLoc(N), VT, N1, N0); in visitFMINNUM()
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D | SelectionDAGBuilder.cpp | 5013 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl, in visitIntrinsicCall() 5985 if (visitBinaryFloatCall(I, ISD::FMINNUM)) in visitCall()
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/external/llvm/lib/CodeGen/ |
D | TargetLoweringBase.cpp | 803 setOperationAction(ISD::FMINNUM, VT, Expand); in initActions() 839 setOperationAction(ISD::FMINNUM, VT, Expand); in initActions()
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/external/llvm/include/llvm/Target/ |
D | TargetSelectionDAG.td | 398 def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp>;
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/external/llvm/lib/Target/PowerPC/ |
D | PPCISelLowering.cpp | 673 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal); in PPCTargetLowering() 719 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal); in PPCTargetLowering()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64ISelLowering.cpp | 315 setOperationAction(ISD::FMINNUM, MVT::f16, Promote); in AArch64TargetLowering()
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/external/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 662 setOperationAction(ISD::FMINNUM, MVT::f80, Expand); in X86TargetLowering()
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