| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUISelLowering.cpp | 37 setOperationAction(ISD::FRINT, MVT::f32, Legal); in AMDGPUTargetLowering()
142 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 499 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, enumerator
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| D | BasicTTIImpl.h | 608 ISD = ISD::FRINT; in getIntrinsicInstrCost()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 290 case Intrinsic::rint: Opcode = ISD::FRINT; break; in mightUseCTR()
343 Opcode = ISD::FRINT; break; in mightUseCTR()
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| D | PPCISelLowering.cpp | 141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand); in PPCTargetLowering()
458 setOperationAction(ISD::FRINT, VT, Expand); in PPCTargetLowering()
765 setOperationAction(ISD::FRINT, MVT::v4f64, Expand); in PPCTargetLowering()
766 setOperationAction(ISD::FRINT, MVT::v4f32, Expand); in PPCTargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedA57.td | 483 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>;
485 def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
556 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT.+r")>;
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| D | AArch64ISelLowering.cpp | 172 setOperationAction(ISD::FRINT, MVT::f128, Expand); in AArch64TargetLowering()
304 setOperationAction(ISD::FRINT, MVT::f16, Promote); in AArch64TargetLowering()
348 setOperationAction(ISD::FRINT, MVT::v4f16, Expand); in AArch64TargetLowering()
380 setOperationAction(ISD::FRINT, MVT::v8f16, Expand); in AArch64TargetLowering()
402 setOperationAction(ISD::FRINT, Ty, Legal); in AArch64TargetLowering()
534 setOperationAction(ISD::FRINT, MVT::v1f64, Expand); in AArch64TargetLowering()
610 setOperationAction(ISD::FRINT, Ty, Legal); in AArch64TargetLowering()
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| D | AArch64SchedCyclone.td | 573 // FRINT(AIMNPXZ) V,V
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.cpp | 127 setOperationAction(ISD::FRINT, MVT::f32, Legal); in AMDGPUTargetLowering()
247 setOperationAction(ISD::FRINT, MVT::f64, Custom); in AMDGPUTargetLowering()
375 setOperationAction(ISD::FRINT, VT, Expand); in AMDGPUTargetLowering()
614 case ISD::FRINT: return LowerFRINT(Op, DAG); in LowerOperation()
1034 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
2022 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0)); in LowerFNEARBYINT()
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| D | SIISelLowering.cpp | 203 setOperationAction(ISD::FRINT, MVT::f64, Legal); in SITargetLowering()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 155 case ISD::FRINT: return "frint"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 94 case ISD::FRINT: R = SoftenFloatRes_FRINT(N); break; in SoftenFloatResult()
907 case ISD::FRINT: ExpandFloatRes_FRINT(N, Lo, Hi); break; in ExpandFloatResult()
1745 case ISD::FRINT: in PromoteFloatResult()
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| D | LegalizeVectorOps.cpp | 313 case ISD::FRINT: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 90 case ISD::FRINT: in ScalarizeVectorResult()
632 case ISD::FRINT: in SplitVectorResult()
1810 case ISD::FRINT: in WidenVectorResult()
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| D | LegalizeDAG.cpp | 3368 case ISD::FRINT: in ExpandNode()
4243 case ISD::FRINT: in PromoteNode()
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| D | SelectionDAGBuilder.cpp | 5002 case Intrinsic::rint: Opcode = ISD::FRINT; break; in visitIntrinsicCall()
6036 if (visitUnaryFloatCall(I, ISD::FRINT)) in visitCall()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 843 setOperationAction(ISD::FRINT, VT, Expand); in initActions()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 317 setOperationAction(ISD::FRINT, Ty, Legal); in addMSAFloatType()
1874 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 477 setOperationAction(ISD::FRINT, MVT::v2f64, Expand); in ARMTargetLowering()
494 setOperationAction(ISD::FRINT, MVT::v4f32, Expand); in ARMTargetLowering()
511 setOperationAction(ISD::FRINT, MVT::v2f32, Expand); in ARMTargetLowering()
615 setOperationAction(ISD::FRINT, MVT::f64, Expand); in ARMTargetLowering()
911 setOperationAction(ISD::FRINT, MVT::f32, Legal); in ARMTargetLowering()
918 setOperationAction(ISD::FRINT, MVT::f64, Legal); in ARMTargetLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 408 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 647 setOperationAction(ISD::FRINT, MVT::f80, Expand); in X86TargetLowering()
700 setOperationAction(ISD::FRINT, VT, Expand); in X86TargetLowering()
945 setOperationAction(ISD::FRINT, RoundedTy, Legal); in X86TargetLowering()
1042 setOperationAction(ISD::FRINT, MVT::v8f32, Legal); in X86TargetLowering()
1055 setOperationAction(ISD::FRINT, MVT::v4f64, Legal); in X86TargetLowering()
1327 setOperationAction(ISD::FRINT, MVT::v16f32, Legal); in X86TargetLowering()
1328 setOperationAction(ISD::FRINT, MVT::v8f64, Legal); in X86TargetLowering()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 260 setOperationAction(ISD::FRINT, VT, Legal); in SystemZTargetLowering()
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| /external/llvm/lib/Target/ |
| D | README.txt | 490 We should add an FRINT node to the DAG to model targets that have legal
|