| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 497 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
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| D | BasicTTIImpl.h | 563 ISD = ISD::FSIN; in getIntrinsicInstrCost()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 149 case ISD::FSIN: return "fsin"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 96 case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break; in SoftenFloatResult()
909 case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi); break; in ExpandFloatResult()
1747 case ISD::FSIN: in PromoteFloatResult()
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| D | LegalizeDAG.cpp | 2325 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN in useSinCos()
2326 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3299 case ISD::FSIN: in ExpandNode()
3302 bool isSIN = Node->getOpcode() == ISD::FSIN; in ExpandNode()
4249 case ISD::FSIN: in PromoteNode()
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| D | LegalizeVectorOps.cpp | 302 case ISD::FSIN: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 92 case ISD::FSIN: in ScalarizeVectorResult()
634 case ISD::FSIN: in SplitVectorResult()
1812 case ISD::FSIN: in WidenVectorResult()
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| D | SelectionDAGBuilder.cpp | 4997 case Intrinsic::sin: Opcode = ISD::FSIN; break; in visitIntrinsicCall()
5997 if (visitUnaryFloatCall(I, ISD::FSIN)) in visitCall()
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| D | DAGCombiner.cpp | 570 case ISD::FSIN: in isNegatibleForFree()
642 case ISD::FSIN: in GetNegatedExpression()
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| /external/llvm/lib/Target/R600/ |
| D | SIISelLowering.cpp | 76 setOperationAction(ISD::FSIN, MVT::f32, Custom); in SITargetLowering()
695 case ISD::FSIN: in LowerOperation()
1235 case ISD::FSIN: in LowerTrig()
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| D | R600ISelLowering.cpp | 65 setOperationAction(ISD::FSIN, MVT::f32, Custom); in R600TargetLowering()
589 case ISD::FSIN: return LowerTrig(Op, DAG); in LowerOperation()
989 case ISD::FSIN: in LowerTrig()
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| D | AMDGPUISelLowering.cpp | 378 setOperationAction(ISD::FSIN, VT, Expand); in AMDGPUTargetLowering()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1417 setOperationAction(ISD::FSIN, MVT::f32, Expand); in HexagonTargetLowering()
1418 setOperationAction(ISD::FSIN, MVT::f64, Expand); in HexagonTargetLowering()
1689 setOperationAction(ISD::FSIN, MVT::f64, Expand); in HexagonTargetLowering()
1692 setOperationAction(ISD::FSIN, MVT::f32, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 173 setOperationAction(ISD::FSIN, MVT::f128, Expand); in AArch64TargetLowering()
275 setOperationAction(ISD::FSIN, MVT::f32, Expand); in AArch64TargetLowering()
276 setOperationAction(ISD::FSIN, MVT::f64, Expand); in AArch64TargetLowering()
305 setOperationAction(ISD::FSIN, MVT::f16, Promote); in AArch64TargetLowering()
349 setOperationAction(ISD::FSIN, MVT::v4f16, Expand); in AArch64TargetLowering()
381 setOperationAction(ISD::FSIN, MVT::v8f16, Expand); in AArch64TargetLowering()
535 setOperationAction(ISD::FSIN, MVT::v1f64, Expand); in AArch64TargetLowering()
638 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand); in addTypeForNEON()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1514 setOperationAction(ISD::FSIN , MVT::f128, Expand); in SparcTargetLowering()
1519 setOperationAction(ISD::FSIN , MVT::f64, Expand); in SparcTargetLowering()
1524 setOperationAction(ISD::FSIN , MVT::f32, Expand); in SparcTargetLowering()
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| /external/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 765 #define FSIN CHOICE(fsin, fsin, fsin) macro
1486 #define FSIN fsin macro
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 465 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); in ARMTargetLowering()
483 setOperationAction(ISD::FSIN, MVT::v4f32, Expand); in ARMTargetLowering()
500 setOperationAction(ISD::FSIN, MVT::v2f32, Expand); in ARMTargetLowering()
604 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
856 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
857 setOperationAction(ISD::FSIN, MVT::f32, Expand); in ARMTargetLowering()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 338 setOperationAction(ISD::FSIN, MVT::f32, Expand); in MipsTargetLowering()
339 setOperationAction(ISD::FSIN, MVT::f64, Expand); in MipsTargetLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 403 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 162 setOperationAction(ISD::FSIN , MVT::f64, Expand); in PPCTargetLowering()
168 setOperationAction(ISD::FSIN , MVT::f32, Expand); in PPCTargetLowering()
451 setOperationAction(ISD::FSIN, VT, Expand); in PPCTargetLowering()
663 setOperationAction(ISD::FSIN , MVT::v4f64, Expand); in PPCTargetLowering()
709 setOperationAction(ISD::FSIN , MVT::v4f32, Expand); in PPCTargetLowering()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 539 setOperationAction(ISD::FSIN , MVT::f64, Expand); in X86TargetLowering()
542 setOperationAction(ISD::FSIN , MVT::f32, Expand); in X86TargetLowering()
569 setOperationAction(ISD::FSIN , MVT::f32, Expand); in X86TargetLowering()
581 setOperationAction(ISD::FSIN , MVT::f64, Expand); in X86TargetLowering()
597 setOperationAction(ISD::FSIN , MVT::f64, Expand); in X86TargetLowering()
598 setOperationAction(ISD::FSIN , MVT::f32, Expand); in X86TargetLowering()
639 setOperationAction(ISD::FSIN , MVT::f80, Expand); in X86TargetLowering()
688 setOperationAction(ISD::FSIN, VT, Expand); in X86TargetLowering()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 272 setOperationAction(ISD::FSIN, VT, Expand); in SystemZTargetLowering()
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| /external/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 1375 setOperationAction(ISD::FSIN, MVT::f32, Expand);
|