/external/llvm/lib/Target/BPF/ |
D | BPFISelDAGToDAG.cpp | 113 case ISD::INTRINSIC_W_CHAIN: { in Select()
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/external/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 145 INTRINSIC_W_CHAIN, enumerator
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D | SelectionDAGNodes.h | 404 return (NodeType == ISD::INTRINSIC_W_CHAIN ||
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/external/llvm/lib/Target/XCore/ |
D | XCoreISelDAGToDAG.cpp | 236 if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN) in SelectBRIND()
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D | XCoreISelLowering.cpp | 183 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN); in XCoreTargetLowering() 1867 case ISD::INTRINSIC_W_CHAIN: in computeKnownBitsForTargetNode()
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/external/llvm/lib/Target/NVPTX/ |
D | NVPTXISelLowering.cpp | 203 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); in NVPTXTargetLowering() 239 setOperationAction(ISD::INTRINSIC_W_CHAIN, VT, Custom); in NVPTXTargetLowering() 244 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom); in NVPTXTargetLowering() 1781 case ISD::INTRINSIC_W_CHAIN: in LowerOperation() 3237 Info.opc = ISD::INTRINSIC_W_CHAIN; in getTgtMemIntrinsic() 3249 Info.opc = ISD::INTRINSIC_W_CHAIN; in getTgtMemIntrinsic() 3263 Info.opc = ISD::INTRINSIC_W_CHAIN; in getTgtMemIntrinsic() 3283 Info.opc = ISD::INTRINSIC_W_CHAIN; in getTgtMemIntrinsic() 4447 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, LdResVTs, Ops, in ReplaceINTRINSIC_W_CHAIN() 4466 case ISD::INTRINSIC_W_CHAIN: in ReplaceNodeResults()
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D | NVPTXISelDAGToDAG.cpp | 155 case ISD::INTRINSIC_W_CHAIN: in Select() 1244 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) { in SelectLDGLDU() 1281 case ISD::INTRINSIC_W_CHAIN: in SelectLDGLDU() 1424 case ISD::INTRINSIC_W_CHAIN: in SelectLDGLDU() 1562 case ISD::INTRINSIC_W_CHAIN: in SelectLDGLDU() 1706 case ISD::INTRINSIC_W_CHAIN: in SelectLDGLDU() 1844 case ISD::INTRINSIC_W_CHAIN: in SelectLDGLDU()
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | SelectionDAGDumper.cpp | 111 case ISD::INTRINSIC_W_CHAIN: { in getOperationName()
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D | TargetLowering.cpp | 1104 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || in computeKnownBitsForTargetNode() 1119 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || in ComputeNumSignBitsForTargetNode()
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D | SelectionDAG.cpp | 2400 case ISD::INTRINSIC_W_CHAIN: in computeKnownBits() 2622 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || in ComputeNumSignBits() 4680 Opcode == ISD::INTRINSIC_W_CHAIN || in getMemIntrinsicNode()
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D | LegalizeDAG.cpp | 1179 case ISD::INTRINSIC_W_CHAIN: in LegalizeOp() 4016 case ISD::INTRINSIC_W_CHAIN: in ExpandNode()
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D | SelectionDAGISel.cpp | 3427 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && in CannotYetSelect()
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D | SelectionDAGBuilder.cpp | 3861 Info.opc == ISD::INTRINSIC_W_CHAIN) in visitTargetIntrinsic() 3890 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops); in visitTargetIntrinsic()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCISelLowering.cpp | 336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom); in PPCTargetLowering() 828 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN); in PPCTargetLowering() 6652 SDValue LoadedVect = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, in LowerBUILD_VECTOR() 7709 case ISD::INTRINSIC_W_CHAIN: return SDValue(); in LowerOperation() 7733 case ISD::INTRINSIC_W_CHAIN: { in ReplaceNodeResults() 8966 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) { in isConsecutiveLS() 9776 case ISD::INTRINSIC_W_CHAIN: { in expandVSXLoadForLE() 10039 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl, in PerformDAGCombine() 10068 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl, in PerformDAGCombine() 10161 case ISD::INTRINSIC_W_CHAIN: { in PerformDAGCombine() [all …]
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/external/llvm/lib/Target/Mips/ |
D | MipsSEISelDAGToDAG.cpp | 789 case ISD::INTRINSIC_W_CHAIN: { in selectNode()
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D | MipsSEISelLowering.cpp | 134 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom); in MipsSETargetLowering() 147 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); in MipsSETargetLowering() 374 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG); in LowerOperation()
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/external/llvm/lib/Target/SystemZ/ |
D | SystemZISelLowering.cpp | 309 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); in SystemZTargetLowering() 1684 if (CmpOp0.getOpcode() == ISD::INTRINSIC_W_CHAIN && in getCmp() 1733 case ISD::INTRINSIC_W_CHAIN: in emitCmp() 2768 case ISD::INTRINSIC_W_CHAIN: in LowerOperation()
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/external/llvm/lib/Target/R600/ |
D | SIISelLowering.cpp | 761 assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN); in LowerBRCOND() 774 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL, in LowerBRCOND()
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/external/llvm/lib/Target/ARM/ |
D | ARMISelLowering.cpp | 555 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN); in ARMTargetLowering() 6243 Cycles32 = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL, in ReplaceREADCYCLECOUNTER() 8756 N->getOpcode() == ISD::INTRINSIC_W_CHAIN); in CombineBaseUpdate() 8977 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN) in CombineVLDDUP() 9833 case ISD::INTRINSIC_W_CHAIN: in PerformDAGCombine() 10418 case ISD::INTRINSIC_W_CHAIN: { in computeKnownBitsForTargetNode() 10890 Info.opc = ISD::INTRINSIC_W_CHAIN; in getTgtMemIntrinsic() 10932 Info.opc = ISD::INTRINSIC_W_CHAIN; in getTgtMemIntrinsic() 10945 Info.opc = ISD::INTRINSIC_W_CHAIN; in getTgtMemIntrinsic() 10957 Info.opc = ISD::INTRINSIC_W_CHAIN; in getTgtMemIntrinsic() [all …]
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D | ARMISelDAGToDAG.cpp | 3012 case ISD::INTRINSIC_W_CHAIN: { in Select()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64ISelLowering.cpp | 496 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN); in AArch64TargetLowering() 723 case ISD::INTRINSIC_W_CHAIN: { in computeKnownBitsForTargetNode() 6452 Info.opc = ISD::INTRINSIC_W_CHAIN; in getTgtMemIntrinsic() 6494 Info.opc = ISD::INTRINSIC_W_CHAIN; in getTgtMemIntrinsic() 6507 Info.opc = ISD::INTRINSIC_W_CHAIN; in getTgtMemIntrinsic() 6519 Info.opc = ISD::INTRINSIC_W_CHAIN; in getTgtMemIntrinsic() 6531 Info.opc = ISD::INTRINSIC_W_CHAIN; in getTgtMemIntrinsic() 8725 case ISD::INTRINSIC_W_CHAIN: in PerformDAGCombine()
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D | AArch64ISelDAGToDAG.cpp | 2214 case ISD::INTRINSIC_W_CHAIN: { in Select()
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/external/llvm/lib/Target/X86/ |
D | X86ISelDAGToDAG.cpp | 1334 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme in SelectAddr() 2087 case ISD::INTRINSIC_W_CHAIN: { in Select()
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonISelDAGToDAG.cpp | 1273 case ISD::INTRINSIC_W_CHAIN: in Select()
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/external/llvm/include/llvm/Target/ |
D | TargetSelectionDAG.td | 519 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
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