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Searched refs:ImmOp (Results 1 – 18 of 18) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoV4.td1234 Operand ImmOp, bits<2>MajOp>
1236 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1316 Operand ImmOp, Operand predImmOp, bits<2> MajOp> {
1319 def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>;
1385 class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp >
1387 (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2),
1396 string ImmOpStr = !cast<string>(ImmOp);
1418 class T_StorePI_nv_pred <string mnemonic, Operand ImmOp,
1422 ImmOp:$offset, IntRegs:$src3),
1433 string ImmOpStr = !cast<string>(ImmOp);
[all …]
DHexagonInstrInfo.td68 class T_CMP <string mnemonic, bits<2> MajOp, bit isNot, Operand ImmOp>
70 (ins IntRegs:$src1, ImmOp:$src2),
1625 Operand ImmOp>
1626 : LDInst<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
1634 string ImmOpStr = !cast<string>(ImmOp);
1657 Operand ImmOp, bit isNot, bit isPredNew>
1659 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1669 string ImmOpStr = !cast<string>(ImmOp);
1699 Operand ImmOp, Operand predImmOp, bits<4>MajOp> {
1702 def L2_#NAME#_io : T_load_io <mnemonic, RC, MajOp, ImmOp>;
[all …]
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
DR600MCCodeEmitter.cpp250 MCOperand ImmOp = MI.getOperand(ImmOpIndex); in EmitSrc() local
251 if (ImmOp.isFPImm()) { in EmitSrc()
252 Value.f = ImmOp.getFPImm(); in EmitSrc()
254 assert(ImmOp.isImm()); in EmitSrc()
255 Value.i = ImmOp.getImm(); in EmitSrc()
/external/llvm/lib/Target/R600/
DSIFoldOperands.cpp262 MachineOperand ImmOp = MachineOperand::CreateImm(Imm.getSExtValue()); in runOnMachineFunction() local
263 tryAddToFoldList(FoldList, UseMI, Use.getOperandNo(), &ImmOp, TII); in runOnMachineFunction()
/external/llvm/lib/Target/ARM/
DThumbRegisterInfo.cpp387 MachineOperand &ImmOp = MI.getOperand(ImmIdx); in rewriteFrameIndex() local
394 ImmOp.ChangeToImmediate(ImmedOffset); in rewriteFrameIndex()
411 ImmOp.ChangeToImmediate(0); in rewriteFrameIndex()
415 ImmOp.ChangeToImmediate(ImmedOffset); in rewriteFrameIndex()
DThumb2InstrInfo.cpp587 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1); in rewriteT2FrameIndex() local
603 ImmOp.ChangeToImmediate(ImmedOffset); in rewriteT2FrameIndex()
621 ImmOp.ChangeToImmediate(ImmedOffset); in rewriteT2FrameIndex()
DARMBaseInstrInfo.cpp2203 MachineOperand &ImmOp = MI.getOperand(ImmIdx); in rewriteARMFrameIndex() local
2218 ImmOp.ChangeToImmediate(ImmedOffset); in rewriteARMFrameIndex()
2231 ImmOp.ChangeToImmediate(ImmedOffset); in rewriteARMFrameIndex()
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp504 struct ImmOp { struct in __anon410038740311::MipsOperand
521 struct ImmOp Imm;
1710 const MCOperand &ImmOp = Inst.getOperand(1); in expandLoadImm() local
1711 assert(ImmOp.isImm() && "expected immediate operand kind"); in expandLoadImm()
1715 int64_t ImmValue = ImmOp.getImm(); in expandLoadImm()
1806 const MCOperand &ImmOp = Inst.getOperand(2); in expandLoadAddressReg() local
1807 assert((ImmOp.isImm() || ImmOp.isExpr()) && in expandLoadAddressReg()
1809 if (!ImmOp.isImm()) { in expandLoadAddressReg()
1817 int ImmValue = ImmOp.getImm(); in expandLoadAddressReg()
1855 const MCOperand &ImmOp = Inst.getOperand(1); in expandLoadAddressImm() local
[all …]
/external/llvm/lib/Target/X86/AsmParser/
DX86Operand.h45 struct ImmOp { struct
62 struct ImmOp Imm;
DX86AsmParser.cpp2055 const MCExpr *ImmOp = MCConstantExpr::Create(ComparisonCode, in ParseInstruction() local
2057 Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc)); in ParseInstruction()
2082 const MCExpr *ImmOp = MCConstantExpr::Create(ComparisonCode, in ParseInstruction() local
2084 Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc)); in ParseInstruction()
2109 const MCExpr *ImmOp = MCConstantExpr::Create(ComparisonCode, in ParseInstruction() local
2111 Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc)); in ParseInstruction()
/external/llvm/lib/Target/X86/
DX86MCInstLower.cpp294 unsigned ImmOp = Inst.getNumOperands() - 1; in SimplifyShortImmForm() local
296 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && in SimplifyShortImmForm()
307 MCOperand Saved = Inst.getOperand(ImmOp); in SimplifyShortImmForm()
/external/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp162 struct ImmOp { struct in __anon818a29540111::SparcOperand
175 struct ImmOp Imm;
/external/llvm/lib/Target/R600/AsmParser/
DAMDGPUAsmParser.cpp73 struct ImmOp { struct in __anon92a627a80111::AMDGPUOperand
87 ImmOp Imm;
/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp188 struct ImmOp { struct in __anon0b51bef40211::AArch64Operand
244 struct ImmOp Imm;
3816 AArch64Operand &ImmOp = static_cast<AArch64Operand &>(*Operands[2]); in MatchAndEmitInstruction() local
3817 if (RegOp.isReg() && ImmOp.isFPImm() && ImmOp.getFPImm() == (unsigned)-1) { in MatchAndEmitInstruction()
/external/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp318 struct ImmOp { struct
333 struct ImmOp Imm;
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp480 struct ImmOp { struct in __anon0735be620311::ARMOperand
551 struct ImmOp Imm;
4713 int CondOp = -1, ImmOp = -1; in cvtThumbBranches() local
4716 case ARM::tBcc: CondOp = 1; ImmOp = 2; break; in cvtThumbBranches()
4719 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break; in cvtThumbBranches()
4752 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); in cvtThumbBranches()
4759 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); in cvtThumbBranches()
4765 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1); in cvtThumbBranches()
/external/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td369 SDPatternOperator ImmOp, InstrItinClass itin> {
374 (OpNode GPR32Opnd:$src, GPR32Opnd:$rs, ImmOp:$sa))];
DMipsSEISelLowering.cpp1401 static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) { in lowerMSASplatImm() argument
1402 return DAG.getConstant(Op->getConstantOperandVal(ImmOp), Op->getValueType(0)); in lowerMSASplatImm()