| /external/clang/include/clang/AST/ |
| D | Attr.h | 54 bool Implicit : 1; variable
80 Inherited(false), IsPackExpansion(false), Implicit(false), in Attr()
100 bool isImplicit() const { return Implicit; } in isImplicit()
101 void setImplicit(bool I) { Implicit = I; } in setImplicit()
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| D | LambdaCapture.h | 62 LambdaCapture(SourceLocation Loc, bool Implicit, LambdaCaptureKind Kind,
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| D | DeclBase.h | 252 unsigned Implicit : 1; variable
319 HasAttrs(false), Implicit(false), Used(false), Referenced(false), in Decl()
329 HasAttrs(false), Implicit(false), Used(false), Referenced(false), in Decl()
498 bool isImplicit() const { return Implicit; } in isImplicit()
499 void setImplicit(bool I = true) { Implicit = I; }
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 32 Implicit = 0x4, enumerator
40 ImplicitDefine = Implicit | Define,
41 ImplicitKill = Implicit | Kill
74 flags & RegState::Implicit,
402 return B ? RegState::Implicit : 0; in getImplRegState()
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| /external/llvm/test/YAMLParser/ |
| D | spec-07-12a.data | 3 # Implicit document. Root
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| D | spec-10-11.data | 6 ? explicit key3, # Implicit empty
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| /external/llvm/lib/Target/R600/ |
| D | SILowerControlFlow.cpp | 402 .addReg(AMDGPU::M0, RegState::Implicit) in IndirectSrc()
403 .addReg(Vec, RegState::Implicit); in IndirectSrc()
424 .addReg(AMDGPU::M0, RegState::Implicit) in IndirectDst()
425 .addReg(Dst, RegState::Implicit); in IndirectDst()
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| D | SIFixSGPRLiveRanges.cpp | 186 .addReg(Reg, RegState::Implicit); in runOnMachineFunction()
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| D | R600InstrInfo.cpp | 71 RegState::Define | RegState::Implicit); in copyPhysReg()
1029 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit); in PredicateInstruction()
1037 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit); in PredicateInstruction()
1138 RegState::Implicit | RegState::Kill); in buildIndirectWrite()
1171 RegState::Implicit | RegState::Kill); in buildIndirectRead()
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| D | SIInstrInfo.cpp | 425 Builder.addReg(DestReg, RegState::Define | RegState::Implicit); in copyPhysReg()
688 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit); in expandPostRAPseudo()
692 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit) in expandPostRAPseudo()
693 .addReg(AMDGPU::SCC, RegState::Implicit); in expandPostRAPseudo()
714 .addReg(Dst, RegState::Implicit); in expandPostRAPseudo()
717 .addReg(Dst, RegState::Implicit); in expandPostRAPseudo()
722 .addReg(Dst, RegState::Implicit); in expandPostRAPseudo()
725 .addReg(Dst, RegState::Implicit); in expandPostRAPseudo()
1857 .addReg(AMDGPU::VCC, RegState::Implicit); in legalizeOperands()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | R600ISelLowering.cpp | 173 .addReg(t0, RegState::Implicit) in EmitInstrWithCustomInserter()
174 .addReg(t1, RegState::Implicit); in EmitInstrWithCustomInserter()
195 .addReg(t0, RegState::Implicit) in EmitInstrWithCustomInserter()
196 .addReg(t1, RegState::Implicit); in EmitInstrWithCustomInserter()
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| D | R600InstrInfo.cpp | 63 .addReg(DestReg, RegState::Define | RegState::Implicit); in copyPhysReg()
463 MachineInstrBuilder(MI).addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit); in PredicateInstruction()
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| /external/eigen/doc/ |
| D | TopicLinearAlgebraDecompositions.dox | 38 <td>Blocking, Implicit MT</td>
249 <dt><b>Implicit Multi Threading (MT)</b></dt>
250 …<dd>Means the algorithm can take advantage of multicore processors via OpenMP. "Implicit" means th…
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| /external/libexif/m4m/ |
| D | gp-packaging.m4 | 41 # FIXME: Implicit dependency
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| D | gp-check-popt.m4 | 56 dnl Implicit AC_SUBST
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| /external/llvm/lib/Target/X86/ |
| D | X86ScheduleSLM.td | 141 // Packed Compare Implicit Length Strings, Return Mask
161 // Packed Compare Implicit Length Strings, Return Index
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| D | X86SchedSandyBridge.td | 161 // Packed Compare Implicit Length Strings, Return Mask
181 // Packed Compare Implicit Length Strings, Return Index
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| D | X86ScheduleBtVer2.td | 248 // Packed Compare Implicit Length Strings, Return Mask
271 // Packed Compare Implicit Length Strings, Return Index
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| D | X86FrameLowering.cpp | 439 CI.addReg(AX, RegState::Implicit) in emitStackProbeCall()
440 .addReg(SP, RegState::Implicit) in emitStackProbeCall()
441 .addReg(AX, RegState::Define | RegState::Implicit) in emitStackProbeCall()
442 .addReg(SP, RegState::Define | RegState::Implicit) in emitStackProbeCall()
443 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); in emitStackProbeCall()
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| D | X86Schedule.td | 99 // Packed Compare Implicit Length Strings, Return Mask
103 // Packed Compare Implicit Length Strings, Return Index
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| /external/clang/test/SemaObjCXX/ |
| D | instantiate-expr.mm | 55 // Implicit setter/getter
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 712 MIB.addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc)); in copyFromCPSR()
734 MIB.addReg(ARM::CPSR, RegState::Implicit | RegState::Define); in copyToCPSR()
1330 MIB.addReg(SrcRegS, RegState::Implicit); in expandPostRAPseudo()
4266 MIB.addReg(SrcReg, RegState::Implicit); in setExecutionDomain()
4297 MIB.addReg(DstReg, RegState::Define | RegState::Implicit); in setExecutionDomain()
4299 MIB.addReg(ImplicitSReg, RegState::Implicit); in setExecutionDomain()
4332 MIB.addReg(DstReg, RegState::Implicit | RegState::Define); in setExecutionDomain()
4333 MIB.addReg(SrcReg, RegState::Implicit); in setExecutionDomain()
4335 MIB.addReg(ImplicitSReg, RegState::Implicit); in setExecutionDomain()
4370 NewMIB.addReg(SrcReg, RegState::Implicit); in setExecutionDomain()
[all …]
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| /external/clang/test/FixIt/ |
| D | format.m | 236 } Implicit;
248 …printf("%f", (Implicit)0); // expected-warning{{format specifies type 'double' but the argument ha…
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 611 .addReg(RegWithZero, RegState::Implicit); in emitCmp()
1166 MIB.addReg(Reg, RegState::Implicit); in fastLowerCall()
1260 MIB.addReg(RetRegs[i], RegState::Implicit); in selectRet()
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| /external/libxml2/vms/ |
| D | readme.vms | 114 - Implicit function warnings. These indicate functions whose type is
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