Searched refs:ImplicitDefine (Results 1 – 20 of 20) sorted by relevance
| /external/llvm/lib/Target/R600/ |
| D | SIPrepareScratchRegs.cpp | 159 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in runOnMachineFunction()
163 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in runOnMachineFunction()
167 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in runOnMachineFunction()
171 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in runOnMachineFunction()
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| D | SIRegisterInfo.cpp | 265 .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); in eliminateFrameIndex()
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| D | SIInstrInfo.cpp | 1849 .addReg(AMDGPU::VCC, RegState::ImplicitDefine); in legalizeOperands()
1856 .addReg(AMDGPU::VCC, RegState::ImplicitDefine) in legalizeOperands()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZElimCompare.cpp | 207 .addReg(SystemZ::CC, RegState::ImplicitDefine); in convertToBRCT()
221 .addReg(SystemZ::CC, RegState::ImplicitDefine); in convertToLoadAndTest()
411 .addReg(SystemZ::CC, RegState::ImplicitDefine); in fuseCompareAndBranch()
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| D | SystemZFrameLowering.cpp | 260 MIB.addReg(Reg, RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 40 ImplicitDefine = Implicit | Define, enumerator
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| /external/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 434 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
578 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
1108 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()
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| D | Thumb2InstrInfo.cpp | 204 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
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| D | ARMBaseInstrInfo.cpp | 1124 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1157 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1178 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1198 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
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| D | ARMFrameLowering.cpp | 1296 .addReg(SupReg, RegState::ImplicitDefine)); in emitAlignedDPRCS2Restores()
1311 .addReg(SupReg, RegState::ImplicitDefine)); in emitAlignedDPRCS2Restores()
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| D | ARMLoadStoreOptimizer.cpp | 665 MIB.addReg(ImpDefs[i], RegState::ImplicitDefine); in MergeOps()
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| D | ARMISelLowering.cpp | 6866 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead); in EmitSjLjDispatchBlock()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 130 .addReg(DestReg, RegState::ImplicitDefine); in copyPhysReg()
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| D | MipsSEISelDAGToDAG.cpp | 50 unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit; in addDSPCtrlRegOperands()
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| D | MipsFastISel.cpp | 607 Mips::FCC0, RegState::ImplicitDefine); in emitCmp()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 802 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine | in EmitMachineNode()
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| /external/llvm/lib/CodeGen/ |
| D | ScheduleDAGInstrs.cpp | 1112 MIB.addReg(*SubRegs, RegState::ImplicitDefine); in toggleKillFlag()
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| /external/llvm/lib/Target/X86/ |
| D | X86FloatingPoint.cpp | 1539 .addReg(X86::ECX, RegState::ImplicitDefine) in handleSpecialFP()
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| D | X86ISelLowering.cpp | 18673 .addReg(X86::RAX, RegState::ImplicitDefine); in EmitLoweredSegAlloca()
18681 .addReg(X86::EAX, RegState::ImplicitDefine); in EmitLoweredSegAlloca()
18689 .addReg(X86::EAX, RegState::ImplicitDefine); in EmitLoweredSegAlloca()
18761 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
18772 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
18783 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
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| D | X86InstrInfo.cpp | 5128 .addReg(Reg, RegState::ImplicitDefine); in breakPartialRegDependency()
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