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Searched refs:InstRWs (Results 1 – 5 of 5) sorted by relevance

/external/llvm/utils/TableGen/
DCodeGenSchedule.cpp562 const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs; in collectSchedClasses()
709 const RecVec &RWDefs = SchedClasses[OldSCIdx].InstRWs; in createInstRWClass()
724 SchedClasses[OldSCIdx].InstRWs.push_back(InstRWDef); in createInstRWClass()
750 for (RecIter RI = SchedClasses[OldSCIdx].InstRWs.begin(), in createInstRWClass()
751 RE = SchedClasses[OldSCIdx].InstRWs.end(); RI != RE; ++RI) { in createInstRWClass()
758 SC.InstRWs.push_back(*RI); in createInstRWClass()
763 SC.InstRWs.push_back(InstRWDef); in createInstRWClass()
848 if (!SchedClasses[Idx].InstRWs.empty()) in inferSchedClasses()
886 for (unsigned I = 0, E = SchedClasses[SCIdx].InstRWs.size(); I != E; ++I) { in inferFromInstRWs()
887 assert(SchedClasses[SCIdx].InstRWs.size() == E && "InstrRWs was mutated!"); in inferFromInstRWs()
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DCodeGenSchedule.h143 RecVec InstRWs; member
DSubtargetEmitter.cpp872 if (!SCI->InstRWs.empty()) { in GenSchedClassTables()
876 for (RecIter RWI = SCI->InstRWs.begin(), RWE = SCI->InstRWs.end(); in GenSchedClassTables()
/external/llvm/lib/Target/AArch64/
DAArch64SchedA53.td194 // Subtarget-specific InstRWs.
DAArch64SchedA57.td63 // evolves, InstRWs will be used to override some of these SchedAliases.