| /external/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.h | 273 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in getHalfSizedIntegerVT() local
274 IntVT <= MVT::LAST_INTEGER_VALUETYPE; ++IntVT) { in getHalfSizedIntegerVT()
275 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 2923 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), in expandFP_TO_SINT() local
2925 SDValue ExponentMask = DAG.getConstant(0x7F800000, IntVT); in expandFP_TO_SINT()
2926 SDValue ExponentLoBit = DAG.getConstant(23, IntVT); in expandFP_TO_SINT()
2927 SDValue Bias = DAG.getConstant(127, IntVT); in expandFP_TO_SINT()
2929 IntVT); in expandFP_TO_SINT()
2930 SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, IntVT); in expandFP_TO_SINT()
2931 SDValue MantissaMask = DAG.getConstant(0x007FFFFF, IntVT); in expandFP_TO_SINT()
2933 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0)); in expandFP_TO_SINT()
2935 SDValue ExponentBits = DAG.getNode(ISD::SRL, dl, IntVT, in expandFP_TO_SINT()
2936 DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask), in expandFP_TO_SINT()
[all …]
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| D | FunctionLoweringInfo.cpp | 539 EVT IntVT = ValueVTs[0]; in ComputePHILiveOutRegInfo() local
541 if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1) in ComputePHILiveOutRegInfo()
543 IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT); in ComputePHILiveOutRegInfo()
544 unsigned BitWidth = IntVT.getSizeInBits(); in ComputePHILiveOutRegInfo()
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| D | FastISel.cpp | 230 EVT IntVT = TLI.getPointerTy(); in materializeConstant() local
233 uint32_t IntBitWidth = IntVT.getSizeInBits(); in materializeConstant()
243 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg, in materializeConstant()
1407 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); in selectFNeg() local
1408 if (!TLI.isTypeLegal(IntVT)) in selectFNeg()
1411 unsigned IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), in selectFNeg()
1417 IntVT.getSimpleVT(), ISD::XOR, IntReg, /*IsKill=*/true, in selectFNeg()
1418 UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT()); in selectFNeg()
1422 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST, in selectFNeg()
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| D | DAGCombiner.cpp | 6984 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); in ConstantFoldBITCASTofBUILD_VECTOR() local
6985 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); in ConstantFoldBITCASTofBUILD_VECTOR()
6986 SrcEltVT = IntVT; in ConstantFoldBITCASTofBUILD_VECTOR()
8254 EVT IntVT = Int.getValueType(); in visitFNEG() local
8255 if (IntVT.isInteger() && !IntVT.isVector()) { in visitFNEG()
8261 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask); in visitFNEG()
8264 SignMask = APInt::getSignBit(IntVT.getSizeInBits()); in visitFNEG()
8266 Int = DAG.getNode(ISD::XOR, SDLoc(N0), IntVT, Int, in visitFNEG()
8267 DAG.getConstant(SignMask, IntVT)); in visitFNEG()
8356 EVT IntVT = Int.getValueType(); in visitFABS() local
[all …]
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| D | SelectionDAG.cpp | 3801 EVT IntVT = VT.getScalarType(); in getMemsetValue() local
3802 if (!IntVT.isInteger()) in getMemsetValue()
3803 IntVT = EVT::getIntegerVT(*DAG.getContext(), IntVT.getSizeInBits()); in getMemsetValue()
3805 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, IntVT, Value); in getMemsetValue()
3810 Value = DAG.getNode(ISD::MUL, dl, IntVT, Value, in getMemsetValue()
3811 DAG.getConstant(Magic, IntVT)); in getMemsetValue()
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| D | SelectionDAGBuilder.cpp | 184 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); in getCopyFromParts() local
185 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V); in getCopyFromParts()
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.cpp | 1547 MVT IntVT = MVT::i32; in LowerDIVREM24() local
1555 IntVT = MVT::getVectorVT(MVT::i32, NElts); in LowerDIVREM24()
1561 SDValue jq = DAG.getConstant(1, IntVT); in LowerDIVREM24()
1574 jq = DAG.getSExtOrTrunc(jq, DL, IntVT); in LowerDIVREM24()
1579 DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT); in LowerDIVREM24()
1583 DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT); in LowerDIVREM24()
1606 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq); in LowerDIVREM24()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 2560 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32; in LowerFormalArguments() local
2561 RegParmTypes.push_back(IntVT); in LowerFormalArguments()
22012 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32; in CMPEQCombine() local
22026 IntVT = MVT::i32; in CMPEQCombine()
22029 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF); in CMPEQCombine()
22030 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI, in CMPEQCombine()
22031 DAG.getConstant(1, IntVT)); in CMPEQCombine()
23622 EVT IntVT = BV->getValueType(0); in performVectorCompareAndMaskUnaryOpCombine() local
23627 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst); in performVectorCompareAndMaskUnaryOpCombine()
23628 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT, in performVectorCompareAndMaskUnaryOpCombine()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 7053 EVT IntVT = BV->getValueType(0); in performVectorCompareAndMaskUnaryOpCombine() local
7058 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst); in performVectorCompareAndMaskUnaryOpCombine()
7059 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT, in performVectorCompareAndMaskUnaryOpCombine()
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