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Searched refs:JALR (Results 1 – 25 of 29) sorted by relevance

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/external/llvm/test/CodeGen/Mips/llvm-ir/
Dret.ll26 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
36 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
46 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
56 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
66 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
76 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
86 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
97 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
112 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
128 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
[all …]
Dindirectbr.ll18 ; R6: jr $4 # <MCInst #{{[0-9]+}} JALR
22 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
27 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
/external/valgrind/none/tests/mips32/
Dbranches.stdout.exp408 J JALR JR :: 6, RSval: 0
409 J JALR JR :: 7, RSval: 1
410 J JALR JR :: 8, RSval: 2
411 J JALR JR :: 9, RSval: 3
412 J JALR JR :: 10, RSval: 4
413 J JALR JR :: 11, RSval: 5
414 J JALR JR :: 12, RSval: 6
415 J JALR JR :: 13, RSval: 7
416 J JALR JR :: 14, RSval: 8
417 J JALR JR :: 15, RSval: 9
[all …]
/external/valgrind/none/tests/mips64/
Dbranches.stdout.exp425 J JALR JR :: 6, RSval: 0
426 J JALR JR :: 7, RSval: 1
427 J JALR JR :: 8, RSval: 2
428 J JALR JR :: 9, RSval: 3
429 J JALR JR :: 10, RSval: 4
430 J JALR JR :: 11, RSval: 5
431 J JALR JR :: 12, RSval: 6
432 J JALR JR :: 13, RSval: 7
433 J JALR JR :: 14, RSval: 8
434 J JALR JR :: 15, RSval: 9
[all …]
/external/v8/src/mips/
Dconstants-mips.cc159 case JALR: in IsForbiddenInBranchDelay()
186 case JALR: in IsLinkingInstruction()
222 case JALR: in InstructionType()
Dassembler-mips.cc540 ((function_field == JALR) || (rd_field == 0 && (function_field == JR)))); in IsJump()
561 GetRdField(instr) == 0 && GetFunctionField(instr) == JALR; in IsJr()
568 GetRdField(instr) != 0 && GetFunctionField(instr) == JALR; in IsJalr()
1435 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR); in jalr()
2668 *(p+2) = SPECIAL | rs_field | rd_field | JALR; in set_target_address_at()
2680 *(p + 2) = SPECIAL | rs_field | (zero_reg.code() << kRdShift) | JALR; in set_target_address_at()
2711 *(p + 2) = SPECIAL | rs_field | rd_field | JALR; in JumpLabelToJumpRegister()
2719 *(p + 2) = SPECIAL | rs_field | (zero_reg.code() << kRdShift) | JALR; in JumpLabelToJumpRegister()
Dassembler-mips-inl.h360 (instr2 & kFunctionFieldMask) == JALR))); in IsPatchedReturnSequence()
Dconstants-mips.h381 JALR = ((1 << 3) + 1), enumerator
Ddisasm-mips.cc635 case JALR: in DecodeTypeRegister()
Dsimulator-mips.cc1921 case JALR: in ConfigureTypeRegister()
2500 case JALR: { in DecodeTypeRegister()
/external/v8/src/mips64/
Dconstants-mips64.cc159 case JALR: in IsForbiddenInBranchDelay()
186 case JALR: in IsLinkingInstruction()
222 case JALR: in InstructionType()
Dassembler-mips64-inl.h357 (instr4 & kFunctionFieldMask) == JALR); in IsPatchedReturnSequence()
Dconstants-mips64.h358 JALR = ((1 << 3) + 1), enumerator
Dassembler-mips64.cc518 ((function_field == JALR) || (rd_field == 0 && (function_field == JR)))); in IsJump()
540 return GetOpcodeField(instr) == SPECIAL && GetFunctionField(instr) == JALR; in IsJalr()
1414 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR); in jalr()
2900 *(p+6) = SPECIAL | rs_field | rd_field | JALR; in JumpLabelToJumpRegister()
Ddisasm-mips64.cc663 case JALR: in DecodeTypeRegister()
Dsimulator-mips64.cc1992 case JALR: in ConfigureTypeRegister()
2621 case JALR: { in DecodeTypeRegister()
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsNaClELFStreamer.cpp51 if (MI.getOpcode() == Mips::JALR) { in isIndirectJump()
81 case Mips::JALR: in isCall()
/external/llvm/test/CodeGen/Mips/
Deh-return32.ll47 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
87 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
Deh-return64.ll48 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
90 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
/external/llvm/lib/Target/Mips/InstPrinter/
DMipsInstPrinter.cpp317 case Mips::JALR: in printAlias()
/external/llvm/lib/Target/Mips/
DMipsInstrInfo.td1314 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1315 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1333 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
1347 // MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the
1564 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1719 // (JALR GPR32:$dst)>;
DMipsDelaySlotFiller.cpp551 case Mips::JALR: in getEquivalentCallShort()
DMipsAsmPrinter.cpp110 TmpInst0.setOpcode(Mips::JALR); in emitPseudoIndirectBranch()
DMips64InstrInfo.td221 def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
/external/pcre/dist/sljit/
DsljitNativeMIPS_common.c142 #define JALR (HI(0) | LO(9)) macro
1721 PTR_FAIL_IF(push_inst(compiler, JALR | S(TMP_REG2) | DA(RETURN_ADDR_REG), UNMOVABLE_INS)); in sljit_emit_jump()
1983 FAIL_IF(push_inst(compiler, JALR | S(PIC_ADDR_REG) | DA(RETURN_ADDR_REG), UNMOVABLE_INS)); in sljit_emit_ijump()
1991 FAIL_IF(push_inst(compiler, JALR | S(src_r) | DA(RETURN_ADDR_REG), UNMOVABLE_INS)); in sljit_emit_ijump()

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