/external/llvm/test/CodeGen/Mips/llvm-ir/ |
D | ret.ll | 26 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 36 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 46 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 56 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 66 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 76 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 86 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 97 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 112 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR 128 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR [all …]
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D | indirectbr.ll | 18 ; R6: jr $4 # <MCInst #{{[0-9]+}} JALR 22 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR 27 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
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/external/valgrind/none/tests/mips32/ |
D | branches.stdout.exp | 408 J JALR JR :: 6, RSval: 0 409 J JALR JR :: 7, RSval: 1 410 J JALR JR :: 8, RSval: 2 411 J JALR JR :: 9, RSval: 3 412 J JALR JR :: 10, RSval: 4 413 J JALR JR :: 11, RSval: 5 414 J JALR JR :: 12, RSval: 6 415 J JALR JR :: 13, RSval: 7 416 J JALR JR :: 14, RSval: 8 417 J JALR JR :: 15, RSval: 9 [all …]
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/external/valgrind/none/tests/mips64/ |
D | branches.stdout.exp | 425 J JALR JR :: 6, RSval: 0 426 J JALR JR :: 7, RSval: 1 427 J JALR JR :: 8, RSval: 2 428 J JALR JR :: 9, RSval: 3 429 J JALR JR :: 10, RSval: 4 430 J JALR JR :: 11, RSval: 5 431 J JALR JR :: 12, RSval: 6 432 J JALR JR :: 13, RSval: 7 433 J JALR JR :: 14, RSval: 8 434 J JALR JR :: 15, RSval: 9 [all …]
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/external/v8/src/mips/ |
D | constants-mips.cc | 159 case JALR: in IsForbiddenInBranchDelay() 186 case JALR: in IsLinkingInstruction() 222 case JALR: in InstructionType()
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D | assembler-mips.cc | 540 ((function_field == JALR) || (rd_field == 0 && (function_field == JR)))); in IsJump() 561 GetRdField(instr) == 0 && GetFunctionField(instr) == JALR; in IsJr() 568 GetRdField(instr) != 0 && GetFunctionField(instr) == JALR; in IsJalr() 1435 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR); in jalr() 2668 *(p+2) = SPECIAL | rs_field | rd_field | JALR; in set_target_address_at() 2680 *(p + 2) = SPECIAL | rs_field | (zero_reg.code() << kRdShift) | JALR; in set_target_address_at() 2711 *(p + 2) = SPECIAL | rs_field | rd_field | JALR; in JumpLabelToJumpRegister() 2719 *(p + 2) = SPECIAL | rs_field | (zero_reg.code() << kRdShift) | JALR; in JumpLabelToJumpRegister()
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D | assembler-mips-inl.h | 360 (instr2 & kFunctionFieldMask) == JALR))); in IsPatchedReturnSequence()
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D | constants-mips.h | 381 JALR = ((1 << 3) + 1), enumerator
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D | disasm-mips.cc | 635 case JALR: in DecodeTypeRegister()
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D | simulator-mips.cc | 1921 case JALR: in ConfigureTypeRegister() 2500 case JALR: { in DecodeTypeRegister()
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/external/v8/src/mips64/ |
D | constants-mips64.cc | 159 case JALR: in IsForbiddenInBranchDelay() 186 case JALR: in IsLinkingInstruction() 222 case JALR: in InstructionType()
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D | assembler-mips64-inl.h | 357 (instr4 & kFunctionFieldMask) == JALR); in IsPatchedReturnSequence()
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D | constants-mips64.h | 358 JALR = ((1 << 3) + 1), enumerator
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D | assembler-mips64.cc | 518 ((function_field == JALR) || (rd_field == 0 && (function_field == JR)))); in IsJump() 540 return GetOpcodeField(instr) == SPECIAL && GetFunctionField(instr) == JALR; in IsJalr() 1414 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR); in jalr() 2900 *(p+6) = SPECIAL | rs_field | rd_field | JALR; in JumpLabelToJumpRegister()
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D | disasm-mips64.cc | 663 case JALR: in DecodeTypeRegister()
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D | simulator-mips64.cc | 1992 case JALR: in ConfigureTypeRegister() 2621 case JALR: { in DecodeTypeRegister()
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
D | MipsNaClELFStreamer.cpp | 51 if (MI.getOpcode() == Mips::JALR) { in isIndirectJump() 81 case Mips::JALR: in isCall()
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/external/llvm/test/CodeGen/Mips/ |
D | eh-return32.ll | 47 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR 87 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
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D | eh-return64.ll | 48 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR 90 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
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/external/llvm/lib/Target/Mips/InstPrinter/ |
D | MipsInstPrinter.cpp | 317 case Mips::JALR: in printAlias()
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/external/llvm/lib/Target/Mips/ |
D | MipsInstrInfo.td | 1314 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM; 1315 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>; 1333 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA. 1347 // MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the 1564 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>; 1719 // (JALR GPR32:$dst)>;
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D | MipsDelaySlotFiller.cpp | 551 case Mips::JALR: in getEquivalentCallShort()
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D | MipsAsmPrinter.cpp | 110 TmpInst0.setOpcode(Mips::JALR); in emitPseudoIndirectBranch()
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D | Mips64InstrInfo.td | 221 def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
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/external/pcre/dist/sljit/ |
D | sljitNativeMIPS_common.c | 142 #define JALR (HI(0) | LO(9)) macro 1721 PTR_FAIL_IF(push_inst(compiler, JALR | S(TMP_REG2) | DA(RETURN_ADDR_REG), UNMOVABLE_INS)); in sljit_emit_jump() 1983 FAIL_IF(push_inst(compiler, JALR | S(PIC_ADDR_REG) | DA(RETURN_ADDR_REG), UNMOVABLE_INS)); in sljit_emit_ijump() 1991 FAIL_IF(push_inst(compiler, JALR | S(src_r) | DA(RETURN_ADDR_REG), UNMOVABLE_INS)); in sljit_emit_ijump()
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