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Searched refs:MInst (Results 1 – 6 of 6) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.cpp188 const MachineInstr *MInst = MII; in EmitInstruction() local
189 if (MInst->getOpcode() == TargetOpcode::DBG_VALUE || in EmitInstruction()
190 MInst->getOpcode() == TargetOpcode::IMPLICIT_DEF) { in EmitInstruction()
196 BundleMIs.push_back(MInst); in EmitInstruction()
DHexagonInstrInfoV3.td195 MInst<(outs DoubleRegs:$Rdd),
218 : MInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
224 MInst <(outs DoubleRegs:$Rxx),
249 : MInst <(outs DoubleRegs:$dst),
260 : MInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
DHexagonInstrInfoV5.td57 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
152 : MInst<(outs IntRegs:$Rd),
217 def F2_sfrecipa: MInst <
696 : MInst<(outs IntRegs:$Rx),
727 def F2_sffma_sc: MInst <
DHexagonInstrFormats.td277 class MInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
288 : MInst<outs, ins, asmstr, pattern, cstr, itin>;
DHexagonInstrInfo.td2336 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
2583 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
2648 : MInst <(outs IntRegs:$dst), (ins RC:$src1, RC:$src2),
2723 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, ImmOp:$u8),
2750 def M2_mpyui : MInst<(outs IntRegs:$dst),
2761 def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
2770 : MInst < (outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, ImmOp:$src3),
2791 : MInst < (outs IntRegs:$dst),
2869 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
2887 : MInst <(outs DoubleRegs:$Rdd),
[all …]
DHexagonInstrInfoV4.td2400 def M4_mpyri_addi : MInst<(outs IntRegs:$Rd),
2426 def M4_mpyrr_addi : MInst <(outs IntRegs:$Rd),
3943 def A4_boundscheck : MInst <