| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 66 MachineRegisterInfo *MRI; member in __anon88d2481e0111::AArch64AdvSIMDScalar
102 const MachineRegisterInfo *MRI) { in isGPR64() argument
106 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
111 const MachineRegisterInfo *MRI) { in isFPR64() argument
113 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()
115 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
125 const MachineRegisterInfo *MRI, in getSrcFromCopy() argument
142 MRI) && in getSrcFromCopy()
143 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
146 MRI) && in getSrcFromCopy()
[all …]
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXCopy.cpp | 58 MachineRegisterInfo &MRI) { in IsRegInClass()
60 return RC->hasSubClassEq(MRI.getRegClass(Reg)); in IsRegInClass()
68 bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSReg()
69 return IsRegInClass(Reg, &PPC::VSRCRegClass, MRI); in IsVSReg()
72 bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVRReg()
73 return IsRegInClass(Reg, &PPC::VRRCRegClass, MRI); in IsVRReg()
76 bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) { in IsF8Reg()
77 return IsRegInClass(Reg, &PPC::F8RCRegClass, MRI); in IsF8Reg()
84 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); in processBlock() local
94 if ( IsVSReg(DstMO.getReg(), MRI) && in processBlock()
[all …]
|
| /external/llvm/lib/Target/R600/ |
| D | SIFixSGPRCopies.cpp | 89 const MachineRegisterInfo &MRI,
93 const MachineRegisterInfo &MRI,
97 const MachineRegisterInfo &MRI) const;
119 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); in hasVGPROperands() local
125 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVGPROperands()
136 const MachineRegisterInfo &MRI, in inferRegClassFromUses() argument
142 MRI.getRegClass(Reg) : in inferRegClassFromUses()
147 I = MRI.use_instr_begin(Reg), E = MRI.use_instr_end(); I != E; ++I) { in inferRegClassFromUses()
150 RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI, in inferRegClassFromUses()
162 const MachineRegisterInfo &MRI, in inferRegClassFromDef() argument
[all …]
|
| D | SIShrinkInstructions.cpp | 76 const MachineRegisterInfo &MRI) { in isVGPR() argument
81 return TRI.hasVGPRs(MRI.getRegClass(MO->getReg())); in isVGPR()
88 const MachineRegisterInfo &MRI) { in canShrink() argument
104 if (Src1 && (!isVGPR(Src1, TRI, MRI) || (Src1Mod && Src1Mod->getImm() != 0))) in canShrink()
127 MachineRegisterInfo &MRI, bool TryToCommute = true) { in foldImmediates() argument
129 if (!MRI.isSSA()) in foldImmediates()
148 if (Src0.isReg() && !isVGPR(&Src0, TRI, MRI)) in foldImmediates()
154 MachineInstr *Def = MRI.getUniqueVRegDef(Reg); in foldImmediates()
164 if (MRI.use_empty(Reg)) in foldImmediates()
174 foldImmediates(MI, TII, MRI, false); in foldImmediates()
[all …]
|
| D | SIInstrInfo.cpp | 904 unsigned Reg, MachineRegisterInfo *MRI) const { in FoldImmediate()
905 if (!MRI->hasOneNonDBGUse(Reg)) in FoldImmediate()
926 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))) in FoldImmediate()
930 (Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))) in FoldImmediate()
967 bool DeleteDef = MRI->hasOneNonDBGUse(Reg); in FoldImmediate()
979 (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg())))) in FoldImmediate()
983 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))) in FoldImmediate()
1003 bool DeleteDef = MRI->hasOneNonDBGUse(Reg); in FoldImmediate()
1224 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI, in usesConstantBus() argument
1235 return RI.isSGPRClass(MRI.getRegClass(MO.getReg())); in usesConstantBus()
[all …]
|
| D | R600OptimizeVectorRegisters.cpp | 50 isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) { in isImplicitlyDef() argument
51 for (MachineRegisterInfo::def_instr_iterator It = MRI.def_instr_begin(Reg), in isImplicitlyDef()
52 E = MRI.def_instr_end(); It != E; ++It) { in isImplicitlyDef()
55 if (MRI.isReserved(Reg)) { in isImplicitlyDef()
67 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) { in RegSeqInfo() argument
72 if (isImplicitlyDef(MRI, MO.getReg())) in RegSeqInfo()
87 MachineRegisterInfo *MRI; member in __anonea54e8c30111::R600VectorRegMerger
191 unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass); in RebuildVector()
218 for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg), in RebuildVector()
219 E = MRI->use_instr_end(); It != E; ++It) { in RebuildVector()
[all …]
|
| D | SILowerI1Copies.cpp | 73 MachineRegisterInfo &MRI = MF.getRegInfo(); in runOnMachineFunction() local
90 const TargetRegisterClass *RC = MRI.getRegClass(Reg); in runOnMachineFunction()
92 MRI.setRegClass(Reg, &AMDGPU::SReg_64RegClass); in runOnMachineFunction()
106 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg()); in runOnMachineFunction()
107 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src.getReg()); in runOnMachineFunction()
114 MachineInstr *DefInst = MRI.getUniqueVRegDef(Src.getReg()); in runOnMachineFunction()
148 MRI.setRegClass(Reg, &AMDGPU::VGPR_32RegClass); in runOnMachineFunction()
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | SIAssignInterpRegs.cpp | 38 void AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI,
90 MachineRegisterInfo &MRI = MF.getRegInfo(); in runOnMachineFunction() local
97 !MRI.use_empty(InterpUse[interp_idx].regs[reg_idx]); in runOnMachineFunction()
113 unsigned virt_reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass); in runOnMachineFunction()
114 MRI.replaceRegWith(InterpUse[interp_idx].regs[reg_idx], virt_reg); in runOnMachineFunction()
115 AddLiveIn(&MF, MRI, new_reg, virt_reg); in runOnMachineFunction()
123 MachineRegisterInfo & MRI, in AddLiveIn() argument
127 if (!MRI.isLiveIn(physReg)) { in AddLiveIn()
128 MRI.addLiveIn(physReg, virtReg); in AddLiveIn()
134 MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg)); in AddLiveIn()
|
| /external/llvm/lib/CodeGen/ |
| D | RegAllocBase.cpp | 61 MRI = &vrm.getRegInfo(); in init()
65 MRI->freezeReservedRegs(vrm.getMachineFunction()); in init()
74 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { in seedLiveRegs()
76 if (MRI->reg_nodbg_empty(Reg)) in seedLiveRegs()
92 if (MRI->reg_nodbg_empty(VirtReg->reg)) { in allocatePhysRegs()
106 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg)) in allocatePhysRegs()
117 I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end(); in allocatePhysRegs()
131 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); in allocatePhysRegs()
142 if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) { in allocatePhysRegs()
|
| D | PeepholeOptimizer.cpp | 113 MachineRegisterInfo *MRI; member in __anone431c6cb0111::PeepholeOptimizer
209 const MachineRegisterInfo &MRI; member in __anone431c6cb0111::ValueTracker
248 const MachineRegisterInfo &MRI, in ValueTracker() argument
252 UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) { in ValueTracker()
254 Def = MRI.getVRegDef(Reg); in ValueTracker()
255 DefIdx = MRI.def_begin(Reg).getOperandNo(); in ValueTracker()
267 const MachineRegisterInfo &MRI, in ValueTracker() argument
271 UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) { in ValueTracker()
326 if (MRI->hasOneNonDBGUse(SrcReg)) in INITIALIZE_PASS_DEPENDENCY()
332 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
[all …]
|
| D | VirtRegMap.cpp | 57 MRI = &mf.getRegInfo(); in runOnMachineFunction()
85 unsigned Hint = MRI->getSimpleHint(VirtReg); in hasPreferredPhys()
94 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg); in hasKnownPreference()
122 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { in print()
127 << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; in print()
131 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { in print()
135 << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; in print()
162 MachineRegisterInfo *MRI; member in __anonc2eabd970111::VirtRegRewriter
211 MRI = &MF->getRegInfo(); in runOnMachineFunction()
235 MRI->clearVirtRegs(); in runOnMachineFunction()
[all …]
|
| D | LLVMTargetMachine.cpp | 46 MRI = TheTarget.createMCRegInfo(getTargetTriple()); in initAsmInfo()
55 MCAsmInfo *TmpAsmInfo = TheTarget.createMCAsmInfo(*MRI, getTargetTriple()); in initAsmInfo()
167 const MCRegisterInfo &MRI = *getMCRegisterInfo(); in addPassesToEmitFile() local
175 Triple(getTargetTriple()), MAI.getAssemblerDialect(), MAI, MII, MRI); in addPassesToEmitFile()
180 MCE = getTarget().createMCCodeEmitter(MII, MRI, *Context); in addPassesToEmitFile()
182 MCAsmBackend *MAB = getTarget().createMCAsmBackend(MRI, getTargetTriple(), in addPassesToEmitFile()
195 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, *Context); in addPassesToEmitFile()
196 MCAsmBackend *MAB = getTarget().createMCAsmBackend(MRI, getTargetTriple(), in addPassesToEmitFile()
243 const MCRegisterInfo &MRI = *getMCRegisterInfo(); in addPassesToEmitMC() local
245 getTarget().createMCCodeEmitter(*getMCInstrInfo(), MRI, *Ctx); in addPassesToEmitMC()
[all …]
|
| D | OptimizePHIs.cpp | 33 MachineRegisterInfo *MRI; member in __anon578c637b0111::OptimizePHIs
69 MRI = &Fn.getRegInfo(); in runOnMachineFunction()
107 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); in IsSingleValuePHICycle()
114 SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg()); in IsSingleValuePHICycle()
147 for (MachineInstr &UseMI : MRI->use_instructions(DstReg)) { in IsDeadPHICycle()
171 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg))) in OptimizeBB()
174 MRI->replaceRegWith(OldReg, SingleValReg); in OptimizeBB()
|
| D | MachineCSE.cpp | 48 MachineRegisterInfo *MRI; member in __anon8b6c16660111::MachineCSE
132 bool OnlyOneUse = MRI->hasOneNonDBGUse(Reg); in INITIALIZE_PASS_DEPENDENCY()
133 MachineInstr *DefMI = MRI->getVRegDef(Reg); in INITIALIZE_PASS_DEPENDENCY()
155 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY()
156 if (!MRI->constrainRegClass(SrcReg, RC)) in INITIALIZE_PASS_DEPENDENCY()
162 MRI->clearKillFlags(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
233 if (!MRI->isConstantPhysReg(Reg, *MBB->getParent())) in hasLivePhysRegDefUses()
285 if (MRI->isAllocatable(PhysDefs[i]) || MRI->isReserved(PhysDefs[i])) in PhysRegDefsReach()
376 for (MachineInstr &MI : MRI->use_nodbg_instructions(CSReg)) { in isProfitableToCSE()
379 for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) { in isProfitableToCSE()
[all …]
|
| D | MachineSink.cpp | 58 MachineRegisterInfo *MRI; // Machine register information member in __anonbe637b600111::MachineSinking
154 !MRI->hasOneNonDBGUse(SrcReg)) in INITIALIZE_PASS_DEPENDENCY()
157 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
158 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
162 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
167 MRI->replaceRegWith(DstReg, SrcReg); in INITIALIZE_PASS_DEPENDENCY()
172 MRI->clearKillFlags(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
192 if (MRI->use_nodbg_empty(Reg)) in AllUsesDominatedByBlock()
211 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { in AllUsesDominatedByBlock()
224 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { in AllUsesDominatedByBlock()
[all …]
|
| D | LiveRangeEdit.cpp | 35 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in createEmptyIntervalFrom()
44 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in createFrom()
94 if (MRI.isConstantPhysReg(MO.getReg(), *OrigMI->getParent()->getParent())) in allUsesAvailableAt()
169 for (MachineOperand &MO : MRI.reg_nodbg_operands(LI->reg)) { in foldAsLoad()
257 if (Reg && MOI->readsReg() && !MRI.isReserved(Reg)) in eliminateDeadDef()
270 (MI->isCopy() || MOI->isDef() || MRI.hasOneNonDBGUse(Reg) || in eliminateDeadDef()
313 if (LIS.hasInterval(Reg) && MRI.reg_nodbg_empty(Reg)) { in eliminateDeadDef()
376 ConEQ.Distribute(&Dups[0], MRI); in eliminateDeadDefs()
402 if (MRI.recomputeRegClass(LI.reg)) in calculateRegClassAndHint()
406 << TRI->getRegClassName(MRI.getRegClass(LI.reg)) << '\n'; in calculateRegClassAndHint()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcFrameLowering.cpp | 110 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); in emitPrologue() local
111 unsigned regFP = MRI->getDwarfRegNum(SP::I6, true); in emitPrologue()
124 unsigned regInRA = MRI->getDwarfRegNum(SP::I7, true); in emitPrologue()
125 unsigned regOutRA = MRI->getDwarfRegNum(SP::O7, true); in emitPrologue()
188 static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI) in verifyLeafProcRegUse() argument
192 if (MRI->isPhysRegUsed(reg)) in verifyLeafProcRegUse()
196 if (MRI->isPhysRegUsed(reg)) in verifyLeafProcRegUse()
205 MachineRegisterInfo &MRI = MF.getRegInfo(); in isLeafProc() local
209 || MRI.isPhysRegUsed(SP::L0) // Too many registers needed in isLeafProc()
210 || MRI.isPhysRegUsed(SP::O6) // %SP is used in isLeafProc()
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 62 MachineRegisterInfo *MRI; member
145 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
163 MachineInstr *MI = MRI->getVRegDef(SReg); in getPrefSPRLane()
230 II = MRI->use_instr_begin(Reg), EE = MRI->use_instr_end(); in eraseInstrWithNoUses()
262 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg()); in optimizeSDPattern()
263 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg()); in optimizeSDPattern()
282 MRI->getRegClass(MI->getOperand(1).getReg()); in optimizeSDPattern()
283 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
314 MachineInstr *Def = MRI->getVRegDef(OpReg); in optimizeSDPattern()
357 MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg()); in elideCopies()
[all …]
|
| D | MLxExpansionPass.cpp | 53 MachineRegisterInfo *MRI; member
95 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
102 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
108 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
120 !MRI->hasOneNonDBGUse(Reg)) in getDefReg()
124 MachineInstr *UseMI = &*MRI->use_instr_nodbg_begin(Reg); in getDefReg()
131 !MRI->hasOneNonDBGUse(Reg)) in getDefReg()
133 UseMI = &*MRI->use_instr_nodbg_begin(Reg); in getDefReg()
149 MachineInstr *DefMI = MRI->getVRegDef(Reg); in hasLoopHazard()
160 DefMI = MRI->getVRegDef(SrcReg); in hasLoopHazard()
[all …]
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFFrameLowering.cpp | 33 MachineRegisterInfo &MRI = MF.getRegInfo(); in processFunctionBeforeCalleeSavedScan() local
35 MRI.setPhysRegUnused(BPF::R6); in processFunctionBeforeCalleeSavedScan()
36 MRI.setPhysRegUnused(BPF::R7); in processFunctionBeforeCalleeSavedScan()
37 MRI.setPhysRegUnused(BPF::R8); in processFunctionBeforeCalleeSavedScan()
38 MRI.setPhysRegUnused(BPF::R9); in processFunctionBeforeCalleeSavedScan()
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCTargetDesc.h | 38 const MCRegisterInfo &MRI,
41 const MCRegisterInfo &MRI,
45 const MCRegisterInfo &MRI, StringRef TT,
48 const MCRegisterInfo &MRI, StringRef TT,
51 const MCRegisterInfo &MRI, StringRef TT,
54 const MCRegisterInfo &MRI, StringRef TT,
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCTargetDesc.h | 60 const MCRegisterInfo &MRI,
64 const MCRegisterInfo &MRI,
67 MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
71 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
74 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
77 MCAsmBackend *createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
80 MCAsmBackend *createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonHardwareLoops.cpp | 65 MachineRegisterInfo *MRI; member
299 MRI = &MF.getRegInfo(); in runOnMachineFunction()
350 MachineInstr *DI = MRI->getVRegDef(PhiOpReg); in findInductionRegister()
358 if (MRI->getVRegDef(IndReg) == Phi) { in findInductionRegister()
377 MachineInstr *PredI = MRI->getVRegDef(PredR); in findInductionRegister()
413 IVOp = MRI->getVRegDef(F->first); in findInductionRegister()
464 MachineInstr *IV_Phi = MRI->getVRegDef(IVReg); in getLoopTripCount()
496 MachineInstr *CondI = MRI->getVRegDef(PredReg); in getLoopTripCount()
588 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent(); in getLoopTripCount()
591 OldInsts.push_back(MRI->getVRegDef(R)); in getLoopTripCount()
[all …]
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 70 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) { in InitLLVM2SEHRegisterMapping() argument
73 unsigned SEH = MRI->getEncodingValue(Reg); in InitLLVM2SEHRegisterMapping()
74 MRI->mapLLVMRegToSEHReg(Reg, SEH); in InitLLVM2SEHRegisterMapping()
118 static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { in createX86MCAsmInfo() argument
148 nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth); in createX86MCAsmInfo()
154 nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth); in createX86MCAsmInfo()
214 const MCRegisterInfo &MRI) { in createX86MCInstPrinter() argument
216 return new X86ATTInstPrinter(MAI, MII, MRI); in createX86MCInstPrinter()
218 return new X86IntelInstPrinter(MAI, MII, MRI); in createX86MCInstPrinter()
|
| /external/llvm/lib/Target/R600/InstPrinter/ |
| D | AMDGPUInstPrinter.cpp | 131 const MCRegisterInfo &MRI) { in printRegOperand() argument
173 if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(reg)) { in printRegOperand()
176 } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(reg)) { in printRegOperand()
179 } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(reg)) { in printRegOperand()
182 } else if (MRI.getRegClass(AMDGPU::SReg_64RegClassID).contains(reg)) { in printRegOperand()
185 } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) { in printRegOperand()
188 } else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) { in printRegOperand()
191 } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) { in printRegOperand()
194 } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(reg)) { in printRegOperand()
197 } else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(reg)) { in printRegOperand()
[all …]
|