| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 296 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 enumerator
687 case X86II::MRM2r: case X86II::MRM3r: in getMemoryOperandNo()
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| D | X86MCCodeEmitter.cpp | 897 case X86II::MRM2r: case X86II::MRM3r: in EmitVEXOpcodePrefix()
1395 case X86II::MRM2r: case X86II::MRM3r: in EncodeInstruction()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrShiftRotate.td | 377 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
379 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
382 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
385 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
387 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
390 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
393 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
395 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
398 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
401 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
[all …]
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| D | X86InstrFPStack.td | 263 def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">;
359 def CMOVP_F : FPI<0xDA, MRM3r, (outs RST:$op), (ins),
367 def CMOVNP_F : FPI<0xDB, MRM3r, (outs RST:$op), (ins),
511 def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RST:$op), "fstp\t$op", IIC_FST>;
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| D | X86InstrSystem.td | 260 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
559 def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
562 def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
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| D | X86InstrArithmetic.td | 377 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
381 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
385 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
389 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
1200 defm SBB : ArithBinOp_RFF<0x18, 0x1A, 0x1C, "sbb", MRM3r, MRM3m, X86sbb_flag,
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| D | X86InstrInfo.td | 2129 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>;
2130 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W;
2345 defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>;
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| D | X86InstrFormats.td | 31 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
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| D | X86InstrSSE.td | 4127 def VPSRLDQri : PDIi8<0x73, MRM3r,
4173 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4219 def PSRLDQri : PDIi8<0x73, MRM3r,
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| /external/llvm/utils/TableGen/ |
| D | X86RecognizableInstr.cpp | 108 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, enumerator
719 case X86Local::MRM3r: in emitInstructionSpecifier()
854 case X86Local::MRM2r: case X86Local::MRM3r: in emitDecodePath()
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| /external/llvm/test/TableGen/ |
| D | TargetInstrInfo.td | 53 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
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| /external/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 1821 case X86II::MRM2r: case X86II::MRM3r: // a REGISTER r/m operand and
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