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Searched refs:PhysReg (Results 1 – 25 of 26) sorted by relevance

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/external/llvm/lib/CodeGen/
DRegAllocFast.cpp73 unsigned PhysReg; // Currently held here. member
78 : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false){} in LiveReg()
124 void markRegUsedInInstr(unsigned PhysReg) { in markRegUsedInInstr() argument
125 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) in markRegUsedInInstr()
130 bool isRegUsedInInstr(unsigned PhysReg) const { in isRegUsedInInstr()
131 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) in isRegUsedInInstr()
177 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
178 unsigned calcSpillCost(unsigned PhysReg) const;
179 void assignVirtToPhysReg(LiveReg&, unsigned PhysReg);
186 LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, unsigned PhysReg);
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DLiveRegMatrix.cpp77 unsigned PhysReg, Callable Func) { in foreachUnit() argument
79 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
91 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
99 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign() argument
101 << " to " << PrintReg(PhysReg, TRI) << ':'); in assign()
103 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); in assign()
104 MRI->setPhysRegUsed(PhysReg); in assign()
106 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, in assign()
118 unsigned PhysReg = VRM->getPhys(VirtReg.reg); in unassign() local
120 << " from " << PrintReg(PhysReg, TRI) << ':'); in unassign()
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DRegAllocGreedy.cpp248 unsigned PhysReg; member
261 PhysReg = Reg; in reset()
342 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg);
347 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
369 unsigned PhysReg, unsigned &CostPerUseLimit,
396 unsigned PhysReg; member
397 HintInfo(BlockFrequency Freq, unsigned Reg, unsigned PhysReg) in HintInfo()
398 : Freq(Freq), Reg(Reg), PhysReg(PhysReg) {} in HintInfo()
597 unsigned PhysReg; in tryAssign() local
598 while ((PhysReg = Order.next())) in tryAssign()
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DRegisterClassInfo.cpp99 unsigned PhysReg = RawOrder[i]; in compute() local
101 if (Reserved.test(PhysReg)) in compute()
103 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute()
106 if (CSRNum[PhysReg]) in compute()
108 CSRAlias.push_back(PhysReg); in compute()
112 RCI.Order[N++] = PhysReg; in compute()
121 unsigned PhysReg = CSRAlias[i]; in compute() local
122 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute()
125 RCI.Order[N++] = PhysReg; in compute()
DInterferenceCache.h42 unsigned PhysReg; variable
97 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(nullptr), LIS(nullptr) {} in Entry()
101 PhysReg = 0; in clear()
107 unsigned getPhysReg() const { return PhysReg; } in getPhysReg()
149 Entry *get(unsigned PhysReg);
202 void setPhysReg(InterferenceCache &Cache, unsigned PhysReg) { in setPhysReg() argument
206 if (PhysReg) in setPhysReg()
207 setEntry(Cache.get(PhysReg)); in setPhysReg()
DVirtRegMap.cpp252 unsigned PhysReg = VRM->getPhys(VirtReg); in addMBBLiveIns() local
253 assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register."); in addMBBLiveIns()
260 for (MCSubRegIndexIterator SR(PhysReg, TRI); SR.isValid(); ++SR) { in addMBBLiveIns()
280 if (!LiveIn[i]->isLiveIn(PhysReg)) in addMBBLiveIns()
281 LiveIn[i]->addLiveIn(PhysReg); in addMBBLiveIns()
361 unsigned PhysReg = VRM->getPhys(VirtReg); in rewrite() local
362 assert(PhysReg != VirtRegMap::NO_PHYS_REG && in rewrite()
364 assert(!MRI->isReserved(PhysReg) && "Reserved register assignment"); in rewrite()
373 SuperKills.push_back(PhysReg); in rewrite()
385 SuperDeads.push_back(PhysReg); in rewrite()
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DInterferenceCache.cpp56 InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) { in get() argument
57 unsigned E = PhysRegEntries[PhysReg]; in get()
58 if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) { in get()
74 Entries[E].reset(PhysReg, LIUArray, TRI, MF); in get()
75 PhysRegEntries[PhysReg] = E; in get()
89 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) in revalidate()
100 PhysReg = physReg; in reset()
106 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in reset()
115 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) { in valid()
186 if (MachineOperand::clobbersPhysReg(RegMaskBits[i], PhysReg)) { in update()
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DRegAllocBasic.cpp111 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
166 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences() argument
173 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in spillInterferences()
185 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) << in spillInterferences()
227 while (unsigned PhysReg = Order.next()) { in selectOrSplit() local
229 switch (Matrix->checkInterference(VirtReg, PhysReg)) { in selectOrSplit()
232 return PhysReg; in selectOrSplit()
236 PhysRegSpillCands.push_back(PhysReg); in selectOrSplit()
DLiveRangeCalc.h115 SlotIndex Kill, unsigned PhysReg);
172 void extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg = 0);
183 void extendToUses(LiveRange &LR, unsigned PhysReg) { in extendToUses() argument
184 extendToUses(LR, PhysReg, ~0u); in extendToUses()
DAllocationOrder.h80 bool isHint(unsigned PhysReg) const { in isHint() argument
81 return std::find(Hints.begin(), Hints.end(), PhysReg) != Hints.end(); in isHint()
DRegisterCoalescer.h66 CoalescerPair(unsigned VirtReg, unsigned PhysReg, in CoalescerPair() argument
68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0), in CoalescerPair()
DLiveRangeCalc.cpp222 void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg) { in extend() argument
238 if (findReachingDefs(LR, *UseMBB, Use, PhysReg)) in extend()
258 SlotIndex Use, unsigned PhysReg) { in findReachingDefs() argument
278 if (TargetRegisterInfo::isPhysicalRegister(PhysReg) && in findReachingDefs()
279 !MBB->isLiveIn(PhysReg)) { in findReachingDefs()
DMachineRegisterInfo.cpp417 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg, in isConstantPhysReg() argument
419 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); in isConstantPhysReg()
423 for (MCRegAliasIterator AI(PhysReg, getTargetRegisterInfo(), true); in isConstantPhysReg()
DMachineBasicBlock.cpp343 MachineBasicBlock::addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC) { in addLiveIn() argument
345 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && "Expected physreg"); in addLiveIn()
350 bool LiveIn = isLiveIn(PhysReg); in addLiveIn()
358 if (I->getOperand(1).getReg() == PhysReg) { in addLiveIn()
368 .addReg(PhysReg, RegState::Kill); in addLiveIn()
370 addLiveIn(PhysReg); in addLiveIn()
/external/llvm/include/llvm/CodeGen/
DLiveRegMatrix.h105 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg);
110 void assign(LiveInterval &VirtReg, unsigned PhysReg);
127 bool checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg = 0);
132 bool checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg);
DRegisterClassInfo.h109 unsigned getLastCalleeSavedAlias(unsigned PhysReg) const { in getLastCalleeSavedAlias() argument
110 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); in getLastCalleeSavedAlias()
111 if (unsigned N = CSRNum[PhysReg]) in getLastCalleeSavedAlias()
DMachineRegisterInfo.h567 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
726 bool canReserveReg(unsigned PhysReg) const { in canReserveReg() argument
727 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg); in canReserveReg()
745 bool isReserved(unsigned PhysReg) const { in isReserved() argument
746 return getReservedRegs().test(PhysReg); in isReserved()
755 bool isAllocatable(unsigned PhysReg) const { in isAllocatable() argument
756 return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) && in isAllocatable()
757 !isReserved(PhysReg); in isAllocatable()
DMachineOperand.h471 static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) { in clobbersPhysReg() argument
473 assert(PhysReg < (1u << 30) && "Not a physical register"); in clobbersPhysReg()
474 return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32)); in clobbersPhysReg()
478 bool clobbersPhysReg(unsigned PhysReg) const { in clobbersPhysReg() argument
479 return clobbersPhysReg(getRegMask(), PhysReg); in clobbersPhysReg()
DMachineBasicBlock.h325 unsigned addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC);
/external/llvm/utils/TableGen/
DFastISelEmitter.cpp426 std::string PhysReg; in PhyRegForNode() local
429 return PhysReg; in PhyRegForNode()
433 return PhysReg; in PhyRegForNode()
435 PhysReg += cast<StringInit>(OpLeafRec->getValue("Namespace")->getValue()) in PhyRegForNode()
437 PhysReg += "::"; in PhyRegForNode()
438 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName(); in PhyRegForNode()
439 return PhysReg; in PhyRegForNode()
542 std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target); in collectPatterns() local
543 if (PhysReg.empty()) { in collectPatterns()
553 PhysRegInputs->push_back(PhysReg); in collectPatterns()
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.cpp113 unsigned &PhysReg, int &Cost) { in CheckForPhysRegDependency() argument
124 PhysReg = Reg; in CheckForPhysRegDependency()
129 PhysReg = Reg; in CheckForPhysRegDependency()
132 if (PhysReg != 0) { in CheckForPhysRegDependency()
468 unsigned PhysReg = 0; in AddSchedEdges() local
471 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost); in AddSchedEdges()
472 assert((PhysReg == 0 || !isChain) && in AddSchedEdges()
480 PhysReg = 0; in AddSchedEdges()
489 : SDep(OpSU, SDep::Data, PhysReg); in AddSchedEdges()
DFunctionLoweringInfo.cpp169 std::pair<unsigned, const TargetRegisterClass *> PhysReg = in set() local
172 if (PhysReg.first == SP) in set()
DSelectionDAGBuilder.cpp6198 std::pair<unsigned, const TargetRegisterClass *> PhysReg = in GetRegistersForValue() local
6209 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { in GetRegistersForValue()
6213 MVT RegVT = *PhysReg.second->vt_begin(); in GetRegistersForValue()
6238 if (unsigned AssignedReg = PhysReg.first) { in GetRegistersForValue()
6239 const TargetRegisterClass *RC = PhysReg.second; in GetRegistersForValue()
6271 if (const TargetRegisterClass *RC = PhysReg.second) { in GetRegistersForValue()
/external/llvm/test/CodeGen/X86/
Dmisched-copy.ll8 ; MUL_HiLo PhysReg use copies should be just above the mul.
9 ; MUL_HiLo PhysReg def copies should be just below the mul.
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp519 struct PhysRegOp PhysReg; member
947 return PhysReg.Num; in getReg()
1192 OS << "PhysReg<" << PhysReg.Num << ">"; in print()

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