| /external/llvm/test/CodeGen/PowerPC/ |
| D | 2010-03-09-indirect-call.ll | 5 ; Indirect calls must use R12 on Darwin (i.e., R12 must contain the address of
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| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 124 ; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
126 ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
164 ; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
166 ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
205 ; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
207 ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
284 ; ALL: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]]
292 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]]
325 ; ALL: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]]
333 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]]
[all …]
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430CallingConv.td | 19 // i16 are returned in registers R15, R14, R13, R12
20 CCIfType<[i16], CCAssignToReg<[R15, R14, R13, R12]>>
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| D | MSP430RegisterInfo.td | 61 def R12 : MSP430RegWithSubregs<12, "r12", [R12B]>;
77 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
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| D | MSP430RegisterInfo.cpp | 55 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
61 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
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| /external/libunwind/src/x86_64/ |
| D | init.h | 61 c->dwarf.loc[R12] = REG_INIT_LOC(c, r12, R12); in common_init()
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| D | Gget_save_loc.c | 43 case UNW_X86_64_R12: loc = c->dwarf.loc[R12]; break; in unw_get_save_loc()
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| D | unwind_i.h | 51 #define R12 12 macro
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| D | Gregs.c | 117 case UNW_X86_64_R12: loc = c->dwarf.loc[R12]; break; in tdep_access_reg()
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| /external/libhevc/decoder/arm/ |
| D | ihevcd_fmt_conv_420sp_to_rgba8888.s | 91 STMFD SP!,{R4-R12,LR}
145 @SUB R12,R8,R3, LSR #1 @// v offset
438 @ADD R2,R2,R12 @// adjust v pointer
448 LDMFD SP!,{R4-R12,PC}
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.h | 41 case R8: case R9: case R10: case R11: case R12: in isARMArea1Register()
52 case R8: case R9: case R10: case R11: case R12: in isARMArea2Register()
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| D | ThumbRegisterInfo.cpp | 462 .addReg(ARM::R12, RegState::Define) in saveScavengerRegister()
475 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::R12)) { in saveScavengerRegister()
483 if (MO.getReg() == ARM::R12) { in saveScavengerRegister()
492 addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill)); in saveScavengerRegister()
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| D | Thumb1FrameLowering.cpp | 212 case ARM::R12: in emitPrologue()
432 .addReg(ARM::R12, RegState::Define) in emitEpilogue()
446 .addReg(ARM::R12, RegState::Kill)); in emitEpilogue()
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| /external/llvm/test/CodeGen/ARM/ |
| D | unaligned_load_store.ll | 18 ; EXPANDED: ldrb [[R12:r[0-9]+]]
21 ; EXPANDED: strb [[R12]]
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| /external/llvm/test/CodeGen/Thumb2/ |
| D | 2010-08-10-VarSizedAllocaBug.ll | 10 ; CHECK: sub.w [[R12:r[0-9]+]], r4, #1000
11 ; CHECK: mov sp, [[R12]]
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| /external/strace/linux/x86_64/ |
| D | userent.h | 4 XLAT(8*R12),
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| /external/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineAndOrXor.cpp | 640 Value *R11,*R12; in foldLogOpOfMaskedICmpsHelper() local
642 if (decomposeBitTestICmp(RHS, RHSCC, R11, R12, R2)) { in foldLogOpOfMaskedICmpsHelper()
644 A = R11; D = R12; in foldLogOpOfMaskedICmpsHelper()
645 } else if (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22) { in foldLogOpOfMaskedICmpsHelper()
646 A = R12; D = R11; in foldLogOpOfMaskedICmpsHelper()
652 if (!match(R1, m_And(m_Value(R11), m_Value(R12)))) { in foldLogOpOfMaskedICmpsHelper()
656 R12 = Constant::getAllOnesValue(R1->getType()); in foldLogOpOfMaskedICmpsHelper()
660 A = R11; D = R12; E = R2; ok = true; in foldLogOpOfMaskedICmpsHelper()
661 } else if (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22) { in foldLogOpOfMaskedICmpsHelper()
662 A = R12; D = R11; E = R2; ok = true; in foldLogOpOfMaskedICmpsHelper()
[all …]
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| /external/kernel-headers/original/uapi/asm-x86/asm/ |
| D | ptrace-abi.h | 31 #define R12 24 macro
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| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 636 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegister()
673 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegister()
709 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegister()
745 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegister()
746 return X86::R12; in getX86SubSuperRegister()
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| D | X86CallingConv.td | 377 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
693 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
698 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
712 R11, R12, R13, R14, R15, RBP,
722 def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
727 R12, R13, R14, R15,
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| /external/valgrind/coregrind/m_sigframe/ |
| D | sigframe-arm-linux.c | 111 SC2(ip,R12); in synth_ucontext()
295 REST(ip,R12); in VG_()
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| /external/valgrind/VEX/orig_ppc32/ |
| D | return0.orig | 248 5: PUTL t4, R12
258 11: GETL R12, t10
561 6: PUTL t2, R12
565 8: GETL R12, t4
571 12: GETL R12, t6
907 8: PUTL t6, R12
911 10: GETL R12, t8
1040 10: PUTL t6, R12
1153 68: GETL R12, t54
1336 41: PUTL t24, R12
[all …]
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| D | date.orig | 248 5: PUTL t4, R12
258 11: GETL R12, t10
561 6: PUTL t2, R12
565 8: GETL R12, t4
571 12: GETL R12, t6
907 8: PUTL t6, R12
911 10: GETL R12, t8
1040 10: PUTL t6, R12
1153 68: GETL R12, t54
1336 41: PUTL t24, R12
[all …]
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| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 183 ENTRY(R12) \
201 ENTRY(R12) \
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| /external/google-breakpad/src/common/android/ |
| D | breakpad_getcontext_unittest.cc | 125 CHECK_REG(R12); in TEST()
|