| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 131 ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
132 ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
171 ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
172 ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
212 ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
213 ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
251 ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
252 ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
291 ; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]]
292 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]]
[all …]
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430CallingConv.td | 19 // i16 are returned in registers R15, R14, R13, R12
20 CCIfType<[i16], CCAssignToReg<[R15, R14, R13, R12]>>
|
| D | MSP430RegisterInfo.td | 64 def R15 : MSP430RegWithSubregs<15, "r15", [R15B]>;
77 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
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| D | MSP430RegisterInfo.cpp | 55 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
61 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
|
| /external/libunwind/src/x86_64/ |
| D | init.h | 64 c->dwarf.loc[R15] = REG_INIT_LOC(c, r15, R15); in common_init()
|
| D | Gget_save_loc.c | 46 case UNW_X86_64_R15: loc = c->dwarf.loc[R15]; break; in unw_get_save_loc()
|
| D | unwind_i.h | 54 #define R15 15 macro
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| D | Gregs.c | 120 case UNW_X86_64_R15: loc = c->dwarf.loc[R15]; break; in tdep_access_reg()
|
| D | Gos-freebsd.c | 126 c->dwarf.loc[R15] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_R15, 0); in unw_handle_signal_frame()
|
| /external/strace/linux/x86_64/ |
| D | userent.h | 1 XLAT(8*R15),
|
| /external/kernel-headers/original/uapi/asm-x86/asm/ |
| D | ptrace-abi.h | 28 #define R15 0 macro
|
| /external/llvm/lib/Target/X86/ |
| D | X86CallingConv.td | 171 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
377 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
390 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
693 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
698 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
712 R11, R12, R13, R14, R15, RBP,
723 R13, R14, R15,
727 R12, R13, R14, R15,
738 def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RDI, RSI, R14, R15,
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| D | X86RegisterInfo.cpp | 642 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegister()
679 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegister()
715 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegister()
751 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegister()
752 return X86::R15; in getX86SubSuperRegister()
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| D | X86RegisterInfo.td | 147 def R15 : X86Reg<"r15", 15, [R15D]>, DwarfRegNum<[15, -2, -2]>;
313 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
345 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
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| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 186 ENTRY(R15)
204 ENTRY(R15)
|
| /external/google-breakpad/src/common/android/ |
| D | breakpad_getcontext_unittest.cc | 128 CHECK_REG(R15); in TEST()
|
| /external/llvm/test/CodeGen/X86/ |
| D | ghc-cc64.ll | 14 @splim = external global i64 ; assigned to register: R15
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| /external/llvm/lib/Target/Hexagon/Disassembler/ |
| D | HexagonDisassembler.cpp | 61 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
|
| /external/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 138 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
149 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86AsmBackend.cpp | 457 case X86::R15: in PushInstrSize()
634 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 in getCompactUnwindRegNum()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 207 def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
216 def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILRegisterInfo.td | 37 def R15 : AMDILReg<15, "r15">, DwarfRegNum<[15]>;
|
| /external/llvm/include/llvm/DebugInfo/PDB/ |
| D | PDBTypes.h | 416 R15 = 343, enumerator
|
| /external/valgrind/coregrind/m_sigframe/ |
| D | sigframe-amd64-linux.c | 352 SC2(r15,R15); in synth_ucontext()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.td | 86 /// together with R14 and R15 in one prolog instruction.
|