| /external/llvm/lib/Target/MSP430/ |
| D | MSP430RegisterInfo.cpp | 44 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
49 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
54 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
60 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
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| D | MSP430RegisterInfo.td | 58 def R9 : MSP430RegWithSubregs<9, "r9", [R9B]>;
77 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.td | 35 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
49 R4, R5, R6, R7, R8, R9, R10,
56 R4, R5, R6, R7, R8, R9, R10,
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| D | XCoreRegisterInfo.cpp | 217 XCore::R8, XCore::R9, XCore::R10, in getCalleeSavedRegs()
222 XCore::R8, XCore::R9, in getCalleeSavedRegs()
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| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 119 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
123 ; ALL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
159 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
163 ; ALL: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
199 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
203 ; ALL: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]
240 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
244 ; ALL: and $[[R18:[0-9]+]], $[[R9]], $[[R7]]
281 ; ALL: andi $[[R9:[0-9]+]], $4, 255
282 ; ALL: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]]
[all …]
|
| /external/valgrind/VEX/orig_ppc32/ |
| D | return0.orig | 100 43: PUTL t30, R9
147 76: GETL R9, t58
152 79: GETL R9, t60
154 81: PUTL t60, R9
172 1: GETL R9, t2
177 4: GETL R9, t4
179 6: PUTL t4, R9
315 52: PUTL t40, R9
319 54: GETL R9, t42
326 59: GETL R9, t46
[all …]
|
| D | date.orig | 100 43: PUTL t30, R9
147 76: GETL R9, t58
152 79: GETL R9, t60
154 81: PUTL t60, R9
172 1: GETL R9, t2
177 4: GETL R9, t4
179 6: PUTL t4, R9
315 52: PUTL t40, R9
319 54: GETL R9, t42
326 59: GETL R9, t46
[all …]
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFRegisterInfo.td | 31 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
37 R6, R7, R8, R9, // callee saved
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| D | BPFFrameLowering.cpp | 38 MRI.setPhysRegUnused(BPF::R9); in processFunctionBeforeCalleeSavedScan()
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| D | BPFCallingConv.td | 29 def CSR : CalleeSavedRegs<(add R6, R7, R8, R9, R10)>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMCallingConv.td | 106 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
205 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
212 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
216 // iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved register.
218 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
221 (sub CSR_AAPCS_ThisReturn, R9))>;
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| D | ARMBaseRegisterInfo.h | 41 case R8: case R9: case R10: case R11: case R12: in isARMArea1Register()
52 case R8: case R9: case R10: case R11: case R12: in isARMArea2Register()
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| /external/libunwind/src/x86_64/ |
| D | init.h | 58 c->dwarf.loc[R9] = REG_INIT_LOC(c, r9, R9); in common_init()
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| D | unwind_i.h | 48 #define R9 9 macro
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| D | Gregs.c | 114 case UNW_X86_64_R9: loc = c->dwarf.loc[R9]; break; in tdep_access_reg()
|
| /external/strace/linux/x86_64/ |
| D | userent.h | 9 XLAT(8*R9),
|
| /external/kernel-headers/original/uapi/asm-x86/asm/ |
| D | ptrace-abi.h | 37 #define R9 64 macro
|
| /external/libhevc/decoder/arm/ |
| D | ihevcd_fmt_conv_420sp_to_rgba8888.s | 139 LDR R9,[sp,#52]
146 SUB R14,R9,R3 @// rgb offset in pixels
153 ADD R8,R2,R9,LSL #2 @// rgb_next_row = rgb + rgb_stride
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| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 630 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: in getX86SubSuperRegister()
667 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: in getX86SubSuperRegister()
703 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: in getX86SubSuperRegister()
739 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: in getX86SubSuperRegister()
740 return X86::R9; in getX86SubSuperRegister()
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| D | X86CallingConv.td | 253 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
332 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
335 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
341 [RCX , RDX , R8 , R9 ]>>,
377 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
618 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>,
703 R8, R9, R10, RSP)>;
711 def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
|
| /external/valgrind/coregrind/m_sigframe/ |
| D | sigframe-arm-linux.c | 108 SC2(r9,R9); in synth_ucontext()
292 REST(r9,R9); in VG_()
|
| /external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/en-US/ |
| D | en-US_lh0_kdt_mgc2.pkb | 69 �������8���[� �����ͅ���k� �R�x0e_������Xl��@���`YD�R9��
|
| /external/llvm/test/Transforms/LowerBitSets/ |
| D | simple.ll | 84 ; CHECK: [[R9:%[^ ]*]] = load i8, i8* [[R8]]
85 ; CHECK: [[R10:%[^ ]*]] = and i8 [[R9]], 1
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 180 ENTRY(R9) \
198 ENTRY(R9) \
|
| /external/google-breakpad/src/common/android/ |
| D | breakpad_getcontext_unittest.cc | 122 CHECK_REG(R9); in TEST()
|