| /external/pcre/dist/testdata/ |
| D | grepoutput | 5 RC=0
8 RC=0
14 RC=0
17 RC=0
26 RC=0
35 RC=0
39 RC=0
42 RC=0
44 RC=0
46 RC=1
[all …]
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXRegisterInfo.cpp | 29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { in getNVPTXRegClassName() argument
30 if (RC == &NVPTX::Float32RegsRegClass) { in getNVPTXRegClassName()
33 if (RC == &NVPTX::Float64RegsRegClass) { in getNVPTXRegClassName()
35 } else if (RC == &NVPTX::Int64RegsRegClass) { in getNVPTXRegClassName()
37 } else if (RC == &NVPTX::Int32RegsRegClass) { in getNVPTXRegClassName()
39 } else if (RC == &NVPTX::Int16RegsRegClass) { in getNVPTXRegClassName()
41 } else if (RC == &NVPTX::Int1RegsRegClass) { in getNVPTXRegClassName()
43 } else if (RC == &NVPTX::SpecialRegsRegClass) { in getNVPTXRegClassName()
51 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) { in getNVPTXRegClassStr() argument
52 if (RC == &NVPTX::Float32RegsRegClass) { in getNVPTXRegClassStr()
[all …]
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| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 67 void compute(const TargetRegisterClass *RC) const;
70 const RCInfo &get(const TargetRegisterClass *RC) const { in get() argument
71 const RCInfo &RCI = RegClass[RC->getID()]; in get()
73 compute(RC); in get()
86 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs() argument
87 return get(RC).NumRegs; in getNumAllocatableRegs()
93 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder() argument
94 return get(RC); in getOrder()
103 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass() argument
104 return get(RC).ProperSubClass; in isProperSubClass()
[all …]
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreMachineFunctionInfo.cpp | 38 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createLRSpillSlot() local
42 LRSpillSlot = MFI->CreateFixedObject(RC->getSize(), 0, true); in createLRSpillSlot()
44 LRSpillSlot = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true); in createLRSpillSlot()
54 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createFPSpillSlot() local
56 FPSpillSlot = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true); in createFPSpillSlot()
65 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createEHSpillSlot() local
67 EHSpillSlot[0] = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true); in createEHSpillSlot()
68 EHSpillSlot[1] = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true); in createEHSpillSlot()
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| /external/llvm/utils/release/ |
| D | test-release.sh | 28 RC=""
75 -rc | --rc | -RC | --RC )
77 RC="rc$1"
80 RC=final
152 if [ -z "$RC" ]; then
176 BuildDir=$BuildDir/$RC
186 if [ $RC != "final" ]; then
187 Package=$Package-$RC
232 if ! svn ls $Base_url/$proj/tags/RELEASE_$Release_no_dot/$RC > /dev/null 2>&1 ; then
233 echo "$proj $Release release candidate $RC doesn't exist!"
[all …]
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| /external/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 88 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { in getAllocatableClass()
89 if (!RC || RC->isAllocatable()) in getAllocatableClass()
90 return RC; in getAllocatableClass()
92 const unsigned *SubClass = RC->getSubClassMask(); in getAllocatableClass()
119 const TargetRegisterClass* RC = *I; in getMinimalPhysRegClass() local
120 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) && in getMinimalPhysRegClass()
121 (!BestRC || BestRC->hasSubClass(RC))) in getMinimalPhysRegClass()
122 BestRC = RC; in getMinimalPhysRegClass()
132 const TargetRegisterClass *RC, BitVector &R){ in getAllocatableSetForRC() argument
133 assert(RC->isAllocatable() && "invalid for nonallocatable sets"); in getAllocatableSetForRC()
[all …]
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| D | RegisterClassInfo.cpp | 79 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { in compute()
80 assert(RC && "no register class given"); in compute()
81 RCInfo &RCI = RegClass[RC->getID()]; in compute()
84 unsigned NumRegs = RC->getNumRegs(); in compute()
97 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF); in compute()
135 TRI->getLargestLegalSuperClass(RC, *MF)) in compute()
136 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
143 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = ["; in compute()
157 const TargetRegisterClass *RC = nullptr; in computePSetLimit() local
172 if (!RC || NUnits > NumRCUnits) { in computePSetLimit()
[all …]
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| D | LiveStackAnalysis.cpp | 60 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { in getOrCreateInterval() argument
68 S2RCMap.insert(std::make_pair(Slot, RC)); in getOrCreateInterval()
72 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC); in getOrCreateInterval()
84 const TargetRegisterClass *RC = getIntervalRegClass(Slot); in print() local
85 if (RC) in print()
86 OS << " [" << TRI->getRegClassName(RC) << "]\n"; in print()
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| D | RegisterScavenging.cpp | 264 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const { in FindUnusedReg()
265 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); in FindUnusedReg()
277 BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) { in getRegsAvailable() argument
279 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); in getRegsAvailable()
367 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, in scavengeRegister() argument
372 TRI->getAllocatableSet(*I->getParent()->getParent(), RC); in scavengeRegister()
384 BitVector Available = getRegsAvailable(RC); in scavengeRegister()
416 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) { in scavengeRegister()
421 RC, TRI); in scavengeRegister()
429 RC, TRI); in scavengeRegister()
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| /external/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 116 for (const auto &RC : RegisterClasses) in runEnums() local
117 OS << " " << RC.getName() << "RegClassID" in runEnums()
118 << " = " << RC.EnumValue << ",\n"; in runEnums()
182 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure() local
183 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure()
188 RC.buildRegUnitSet(RegUnits); in EmitRegUnitPressure()
192 OS << "}, \t// " << RC.getName() << "\n"; in EmitRegUnitPressure()
957 for (const auto &RC : RegisterClasses) { in runMCDesc() local
958 ArrayRef<Record*> Order = RC.getOrder(); in runMCDesc()
961 std::string Name = RC.getName(); in runMCDesc()
[all …]
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| D | CodeGenRegisters.cpp | 856 CodeGenRegisterClass &RC = *I; in computeSubClasses() local
857 RC.SubClasses.resize(RegClasses.size()); in computeSubClasses()
858 RC.SubClasses.set(RC.EnumValue); in computeSubClasses()
863 if (RC.SubClasses.test(SubRC.EnumValue)) in computeSubClasses()
865 if (!testSubClass(&RC, &SubRC)) in computeSubClasses()
869 RC.SubClasses |= SubRC.SubClasses; in computeSubClasses()
873 for (auto I2 = std::next(I); I2 != E && testSubClass(&RC, &*I2); ++I2) in computeSubClasses()
874 RC.SubClasses.set(I2->EnumValue); in computeSubClasses()
878 for (auto &RC : RegClasses) { in computeSubClasses() local
879 const BitVector &SC = RC.getSubClasses(); in computeSubClasses()
[all …]
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 127 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass() argument
128 return RC != this && hasSubClassEq(RC); in hasSubClass()
133 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq() argument
134 unsigned ID = RC->getID(); in hasSubClassEq()
140 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass() argument
141 return RC->hasSubClass(this); in hasSuperClass()
146 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq() argument
147 return RC->hasSubClassEq(this); in hasSuperClassEq()
323 getAllocatableClass(const TargetRegisterClass *RC) const;
329 const TargetRegisterClass *RC = nullptr) const;
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsMachineFunction.cpp | 77 const TargetRegisterClass *RC = in getGlobalBaseReg() local
87 return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC); in getGlobalBaseReg()
98 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass; in getMips16SPAliasReg() local
99 return Mips16SPAliasReg = MF.getRegInfo().createVirtualRegister(RC); in getMips16SPAliasReg()
104 const TargetRegisterClass *RC = in createEhDataRegsFI() local
109 EhDataRegFI[I] = MF.getFrameInfo()->CreateStackObject(RC->getSize(), in createEhDataRegsFI()
110 RC->getAlignment(), false); in createEhDataRegsFI()
137 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) { in getMoveF64ViaSpillFI() argument
140 RC->getSize(), RC->getAlignment(), false); in getMoveF64ViaSpillFI()
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| D | MipsCondMov.td | 35 class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
37 InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F),
39 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
45 class CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
47 InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F),
49 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
270 class Select_Pseudo<RegisterOperand RC> :
271 PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),
272 [(set RC:$dst, (select GPR32Opnd:$cond, RC:$T, RC:$F))]>,
275 class SelectFP_Pseudo_T<RegisterOperand RC> :
[all …]
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| D | MipsSEFrameLowering.cpp | 155 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() local
156 unsigned VR = MRI.createVirtualRegister(RC); in expandLoadCCond()
159 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); in expandLoadCCond()
170 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() local
171 unsigned VR = MRI.createVirtualRegister(RC); in expandStoreCCond()
176 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); in expandStoreCCond()
188 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() local
189 unsigned VR0 = MRI.createVirtualRegister(RC); in expandLoadACC()
190 unsigned VR1 = MRI.createVirtualRegister(RC); in expandLoadACC()
197 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0); in expandLoadACC()
[all …]
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| D | MipsInstrFPU.td | 102 class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
104 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
106 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr> {
165 class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
167 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
168 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
173 class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
175 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
176 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
181 class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
[all …]
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| D | MipsSEInstrInfo.cpp | 182 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, in storeRegToStack() argument
190 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
192 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
194 else if (Mips::ACC64RegClass.hasSubClassEq(RC)) in storeRegToStack()
196 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) in storeRegToStack()
198 else if (Mips::ACC128RegClass.hasSubClassEq(RC)) in storeRegToStack()
200 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) in storeRegToStack()
202 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
204 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
206 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrFMA.td | 131 RegisterClass RC, ValueType OpVT, PatFrag mem_frag,
135 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
136 (ins RC:$src1, RC:$src2, RC:$src3),
139 [(set RC:$dst,
140 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
143 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
144 (ins RC:$src1, RC:$src2, x86memop:$src3),
147 [(set RC:$dst,
148 (OpVT (OpNode RC:$src2, RC:$src1,
155 SDNode OpNode, RegisterClass RC, ValueType OpVT,
[all …]
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| D | X86InstrAVX512.td | 23 RegisterClass RC = rc;
62 // Size of RC in bits, e.g. 512 for VR512.
131 // "x" in v32i8x_info means RC = VR256X
226 [(set _.RC:$dst, RHS)],
227 [(set _.RC:$dst, MaskingRHS)],
228 [(set _.RC:$dst,
242 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
245 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
257 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
260 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
[all …]
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| /external/llvm/lib/Target/R600/ |
| D | SIFixSGPRCopies.cpp | 140 const TargetRegisterClass *RC in inferRegClassFromUses() local
145 RC = TRI->getSubRegClass(RC, SubReg); in inferRegClassFromUses()
150 RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI, in inferRegClassFromUses()
157 return RC; in inferRegClassFromUses()
166 const TargetRegisterClass *RC = TRI->getPhysRegClass(Reg); in inferRegClassFromDef() local
167 return TRI->getSubRegClass(RC, SubReg); in inferRegClassFromDef()
230 const TargetRegisterClass *RC in runOnMachineFunction() local
233 MRI.constrainRegClass(Op.getReg(), RC); in runOnMachineFunction()
236 const TargetRegisterClass *RC = inferRegClassFromUses(TRI, MRI, Reg, in runOnMachineFunction() local
238 if (TRI->getCommonSubClass(RC, &AMDGPU::VGPR_32RegClass)) { in runOnMachineFunction()
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| D | SIRegisterInfo.h | 51 bool isSGPRClass(const TargetRegisterClass *RC) const { in isSGPRClass()
52 if (!RC) in isSGPRClass()
55 return !hasVGPRs(RC); in isSGPRClass()
67 bool hasVGPRs(const TargetRegisterClass *RC) const;
76 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
120 const TargetRegisterClass *RC) const;
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 369 const TargetRegisterClass *RC = *I; in regPressureDelta() local
370 RegBalance += rawRegPressureDelta(SU, RC->getID()); in regPressureDelta()
376 const TargetRegisterClass *RC = *I; in regPressureDelta() local
377 if ((RegPressure[RC->getID()] + in regPressureDelta()
378 rawRegPressureDelta(SU, RC->getID()) > 0) && in regPressureDelta()
379 (RegPressure[RC->getID()] + in regPressureDelta()
380 rawRegPressureDelta(SU, RC->getID()) >= RegLimit[RC->getID()])) in regPressureDelta()
381 RegBalance += rawRegPressureDelta(SU, RC->getID()); in regPressureDelta()
489 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
490 if (RC) in scheduledNode()
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 115 const TargetRegisterClass *RC,
119 const TargetRegisterClass *RC,
122 const TargetRegisterClass *RC,
153 const TargetRegisterClass *RC, bool IsZExt = true,
165 const TargetRegisterClass *RC);
167 const TargetRegisterClass *RC);
433 const TargetRegisterClass *RC, in PPCEmitLoad() argument
447 (RC ? RC : in PPCEmitLoad()
576 const TargetRegisterClass *RC = in SelectLoad() local
580 if (!PPCEmitLoad(VT, ResultReg, Addr, RC)) in SelectLoad()
[all …]
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| D | PPCInstrInfo.cpp | 611 const TargetRegisterClass *RC = in canInsertSelect() local
613 if (!RC) in canInsertSelect()
617 if (!PPC::GPRCRegClass.hasSubClassEq(RC) && in canInsertSelect()
618 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) && in canInsertSelect()
619 !PPC::G8RCRegClass.hasSubClassEq(RC) && in canInsertSelect()
620 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) in canInsertSelect()
647 const TargetRegisterClass *RC = in insertSelect() local
649 assert(RC && "TrueReg and FalseReg must have overlapping register classes"); in insertSelect()
651 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) || in insertSelect()
652 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC); in insertSelect()
[all …]
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| /external/llvm/test/TableGen/ |
| D | usevalname.td | 18 multiclass shuffle<Reg RC> {
19 def rri : Instr<[(set RC:$dst, (shufp:$src3
20 RC:$src1, RC:$src2))]>;
|