| /external/llvm/lib/Target/R600/ |
| D | R600OptimizeVectorRegisters.cpp | 80 bool operator==(const RegSeqInfo &RSI) const { in operator ==()
81 return RSI.Instr == Instr; in operator ==()
95 bool tryMergeUsingCommonSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
97 bool tryMergeUsingFreeSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
103 void trackRSI(const RegSeqInfo &RSI);
179 RegSeqInfo *RSI, const RegSeqInfo *BaseRSI, in RebuildVector() argument
181 unsigned Reg = RSI->Instr->getOperand(0).getReg(); in RebuildVector()
182 MachineBasicBlock::iterator Pos = RSI->Instr; in RebuildVector()
189 for (DenseMap<unsigned, unsigned>::iterator It = RSI->RegToChan.begin(), in RebuildVector()
190 E = RSI->RegToChan.end(); It != E; ++It) { in RebuildVector()
[all …]
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| /external/libunwind/src/x86_64/ |
| D | init.h | 53 c->dwarf.loc[RSI] = REG_INIT_LOC(c, rsi, RSI); in common_init()
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| D | unwind_i.h | 43 #define RSI 4 macro
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| D | Gregs.c | 111 case UNW_X86_64_RSI: loc = c->dwarf.loc[RSI]; break; in tdep_access_reg()
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| D | Gos-freebsd.c | 115 c->dwarf.loc[RSI] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_RSI, 0); in unw_handle_signal_frame()
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| /external/strace/linux/x86_64/ |
| D | userent.h | 14 XLAT(8*RSI),
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| /external/kernel-headers/original/uapi/asm-x86/asm/ |
| D | ptrace-abi.h | 42 #define RSI 104 macro
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| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 592 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegister()
620 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegister()
657 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegister()
693 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegister()
729 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegister()
730 return X86::RSI; in getX86SubSuperRegister()
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| D | X86CallingConv.td | 253 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
377 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
390 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
621 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>,
698 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
702 def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI,
711 def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
722 def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
726 def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI,
738 def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RDI, RSI, R14, R15,
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| D | X86SelectionDAGInfo.cpp | 232 const unsigned ClobberSet[] = {X86::RCX, X86::RSI, X86::RDI, in EmitTargetCodeForMemcpy()
263 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RSI : in EmitTargetCodeForMemcpy()
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| D | X86InstrSystem.td | 523 let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
531 let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
535 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
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| D | X86RegisterInfo.td | 133 def RSI : X86Reg<"rsi", 6, [ESI]>, DwarfRegNum<[4, -2, -2]>;
344 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
370 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,
391 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
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| /external/llvm/utils/TableGen/ |
| D | CodeGenSchedule.cpp | 1034 RSI = PTI->ReadSequences.begin(), RSE = PTI->ReadSequences.end(); in hasVariant() local
1035 RSI != RSE; ++RSI) { in hasVariant()
1037 RI = RSI->begin(), RE = RSI->end(); RI != RE; ++RI) { in hasVariant()
1271 RSI = Trans.ReadSequences.begin(), RSE = Trans.ReadSequences.end(); in substituteVariants() local
1272 RSI != RSE; ++RSI) { in substituteVariants()
1278 substituteVariantOperand(*RSI, /*IsRead=*/true, StartIdx); in substituteVariants()
1300 RSI = I->ReadSequences.begin(), RSE = I->ReadSequences.end(); in inferFromTransitions() local
1301 RSI != RSE; ++RSI) { in inferFromTransitions()
1304 SchedModels.findOrInsertRW(*RSI, /*IsRead=*/true)); in inferFromTransitions()
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| /external/llvm/test/tools/llvm-objdump/ |
| D | win64-unwind-data.test | 22 OBJ-NEXT: 0x09: UOP_SaveNonVol RSI [0x0010]
71 EXE-NEXT: 0x09: UOP_SaveNonVol RSI [0x0010]
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| /external/lzma/Asm/x86/ |
| D | 7zAsm.asm | 68 r6 equ RSI
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| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 177 ENTRY(RSI) \
195 ENTRY(RSI) \
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| /external/google-breakpad/src/common/android/ |
| D | breakpad_getcontext_unittest.cc | 130 CHECK_REG(RSI); in TEST()
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86Operand.h | 273 (getMemBaseReg() == X86::RSI || getMemBaseReg() == X86::ESI || in isSrcIdx()
379 case X86::RSI: return X86::ESI; in getGR32FromGR64()
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| /external/llvm/test/CodeGen/X86/ |
| D | ghc-cc64.ll | 10 @r3 = external global i64 ; assigned to register: RSI
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| /external/llvm/include/llvm/DebugInfo/PDB/ |
| D | PDBTypes.h | 405 RSI = 332, enumerator
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| /external/valgrind/coregrind/m_sigframe/ |
| D | sigframe-amd64-linux.c | 354 SC2(rsi,RSI); in synth_ucontext()
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| /external/llvm/test/DebugInfo/X86/ |
| D | reference-argument.ll | 6 ; CHECK: ##DEBUG_VALUE: foo:v <- RSI
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| /external/clang/lib/Sema/ |
| D | SemaStmt.cpp | 3845 CapturedRegionScopeInfo *RSI = getCurCapturedRegion(); in ActOnCapturedRegionError() local
3846 RecordDecl *Record = RSI->TheRecordDecl; in ActOnCapturedRegionError()
3858 CapturedRegionScopeInfo *RSI = getCurCapturedRegion(); in ActOnCapturedRegionEnd() local
3862 buildCapturedStmtCaptureList(Captures, CaptureInits, RSI->Captures); in ActOnCapturedRegionEnd()
3864 CapturedDecl *CD = RSI->TheCapturedDecl; in ActOnCapturedRegionEnd()
3865 RecordDecl *RD = RSI->TheRecordDecl; in ActOnCapturedRegionEnd()
3868 RSI->CapRegionKind, Captures, in ActOnCapturedRegionEnd()
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| /external/llvm/lib/DebugInfo/PDB/ |
| D | PDBExtras.cpp | 131 CASE_OUTPUT_ENUM_CLASS_NAME(PDB_RegisterId, RSI, OS) in operator <<()
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| /external/valgrind/VEX/auxprogs/ |
| D | genoffsets.c | 108 GENOFFSET(AMD64,amd64,RSI); in foo()
|