| /external/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 41 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { in setRegClass() argument
43 VRegInfo[Reg].first = RC; in setRegClass()
47 MachineRegisterInfo::constrainRegClass(unsigned Reg, in constrainRegClass() argument
50 const TargetRegisterClass *OldRC = getRegClass(Reg); in constrainRegClass()
59 setRegClass(Reg, NewRC); in constrainRegClass()
64 MachineRegisterInfo::recomputeRegClass(unsigned Reg) { in recomputeRegClass() argument
66 const TargetRegisterClass *OldRC = getRegClass(Reg); in recomputeRegClass()
75 for (MachineOperand &MO : reg_nodbg_operands(Reg)) { in recomputeRegClass()
84 setRegClass(Reg, NewRC); in recomputeRegClass()
98 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); in createVirtualRegister() local
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| D | AggressiveAntiDepBreaker.cpp | 60 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { in GetGroup() argument
61 unsigned Node = GroupNodeIndices[Reg]; in GetGroup()
73 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local
74 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) in GetGroupRegs()
75 Regs.push_back(Reg); in GetGroupRegs()
95 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) in LeaveGroup() argument
102 GroupNodeIndices[Reg] = idx; in LeaveGroup()
106 bool AggressiveAntiDepState::IsLive(unsigned Reg) in IsLive() argument
110 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u)); in IsLive()
155 unsigned Reg = *AI; in StartBlock() local
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| D | LiveVariables.cpp | 182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) { in HandleVirtRegDef() argument
183 VarInfo &VRInfo = getVarInfo(Reg); in HandleVirtRegDef()
192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, in FindLastPartialDef() argument
197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in FindLastPartialDef()
219 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
231 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { in HandlePhysRegUse() argument
232 MachineInstr *LastDef = PhysRegDef[Reg]; in HandlePhysRegUse()
234 if (!LastDef && !PhysRegUse[Reg]) { in HandlePhysRegUse()
244 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs); in HandlePhysRegUse()
247 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
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| D | CriticalAntiDepBreaker.cpp | 63 unsigned Reg = *AI; in StartBlock() local
64 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
65 KillIndices[Reg] = BBSize; in StartBlock()
66 DefIndices[Reg] = ~0u; in StartBlock()
78 unsigned Reg = *AI; in StartBlock() local
79 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
80 KillIndices[Reg] = BBSize; in StartBlock()
81 DefIndices[Reg] = ~0u; in StartBlock()
104 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe() local
105 if (KillIndices[Reg] != ~0u) { in Observe()
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| D | MachineInstrBundle.cpp | 134 unsigned Reg = MO.getReg(); in finalizeBundle() local
135 if (!Reg) in finalizeBundle()
137 assert(TargetRegisterInfo::isPhysicalRegister(Reg)); in finalizeBundle()
138 if (LocalDefSet.count(Reg)) { in finalizeBundle()
142 KilledDefSet.insert(Reg); in finalizeBundle()
144 if (ExternUseSet.insert(Reg).second) { in finalizeBundle()
145 ExternUses.push_back(Reg); in finalizeBundle()
147 UndefUseSet.insert(Reg); in finalizeBundle()
151 KilledUseSet.insert(Reg); in finalizeBundle()
157 unsigned Reg = MO.getReg(); in finalizeBundle() local
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| D | MachineVerifier.cpp | 91 void addRegWithSubRegs(RegVector &RV, unsigned Reg) { in addRegWithSubRegs()
92 RV.push_back(Reg); in addRegWithSubRegs()
93 if (TargetRegisterInfo::isPhysicalRegister(Reg)) in addRegWithSubRegs()
94 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) in addRegWithSubRegs()
129 bool addPassed(unsigned Reg) { in addPassed()
130 if (!TargetRegisterInfo::isVirtualRegister(Reg)) in addPassed()
132 if (regsKilled.count(Reg) || regsLiveOut.count(Reg)) in addPassed()
134 return vregsPassed.insert(Reg).second; in addPassed()
148 bool addRequired(unsigned Reg) { in addRequired()
149 if (!TargetRegisterInfo::isVirtualRegister(Reg)) in addRequired()
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| D | RegisterPressure.cpp | 150 const LiveRange *RegPressureTracker::getLiveRange(unsigned Reg) const { in getLiveRange()
151 if (TargetRegisterInfo::isVirtualRegister(Reg)) in getLiveRange()
152 return &LIS->getInterval(Reg); in getLiveRange()
153 return LIS->getCachedRegUnit(Reg); in getLiveRange()
293 unsigned Reg = P.LiveOutRegs[i]; in initLiveThru() local
294 if (TargetRegisterInfo::isVirtualRegister(Reg) in initLiveThru()
295 && !RPTracker.hasUntiedDef(Reg)) { in initLiveThru()
296 increaseSetPressure(LiveThruPressure, MRI->getPressureSets(Reg)); in initLiveThru()
343 void pushRegUnits(unsigned Reg, SmallVectorImpl<unsigned> &RegUnits) { in pushRegUnits() argument
344 if (TargetRegisterInfo::isVirtualRegister(Reg)) { in pushRegUnits()
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| D | RegisterScavenging.cpp | 34 void RegScavenger::setRegUsed(unsigned Reg) { in setRegUsed() argument
35 for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) in setRegUsed()
42 I->Reg = 0; in initRegState()
92 void RegScavenger::addRegUnits(BitVector &BV, unsigned Reg) { in addRegUnits() argument
93 for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) in addRegUnits()
130 unsigned Reg = MO.getReg(); in determineKillsAndDefs() local
131 if (!Reg || TargetRegisterInfo::isVirtualRegister(Reg) || isReserved(Reg)) in determineKillsAndDefs()
139 addRegUnits(KillRegUnits, Reg); in determineKillsAndDefs()
143 addRegUnits(KillRegUnits, Reg); in determineKillsAndDefs()
145 addRegUnits(DefRegUnits, Reg); in determineKillsAndDefs()
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| D | RegAllocFast.cpp | 710 unsigned Reg = MO.getReg(); in handleThroughOperands() local
711 if (!TargetRegisterInfo::isVirtualRegister(Reg)) in handleThroughOperands()
714 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) { in handleThroughOperands()
715 if (ThroughRegs.insert(Reg).second) in handleThroughOperands()
716 DEBUG(dbgs() << ' ' << PrintReg(Reg)); in handleThroughOperands()
726 unsigned Reg = MO.getReg(); in handleThroughOperands() local
727 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; in handleThroughOperands()
728 markRegUsedInInstr(Reg); in handleThroughOperands()
729 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { in handleThroughOperands()
740 unsigned Reg = MO.getReg(); in handleThroughOperands() local
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| D | LivePhysRegs.cpp | 43 unsigned Reg = O->getReg(); in stepBackward() local
44 if (Reg == 0) in stepBackward()
46 removeReg(Reg); in stepBackward()
55 unsigned Reg = O->getReg(); in stepBackward() local
56 if (Reg == 0) in stepBackward()
58 addReg(Reg); in stepBackward()
71 unsigned Reg = O->getReg(); in stepForward() local
72 if (Reg == 0) in stepForward()
76 Defs.push_back(Reg); in stepForward()
81 removeReg(Reg); in stepForward()
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| D | StackMaps.cpp | 78 static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) { in getDwarfRegNum() argument
79 int RegNo = TRI->getDwarfRegNum(Reg, false); in getDwarfRegNum()
80 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNo < 0; ++SR) in getDwarfRegNum()
99 unsigned Reg = (++MOI)->getReg(); in parseOperand() local
102 getDwarfRegNum(Reg, TRI), Imm)); in parseOperand()
108 unsigned Reg = (++MOI)->getReg(); in parseOperand() local
111 getDwarfRegNum(Reg, TRI), Imm)); in parseOperand()
178 OS << TRI->getName(Loc.Reg); in print()
180 OS << Loc.Reg; in print()
185 OS << TRI->getName(Loc.Reg); in print()
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| D | InlineSpiller.cpp | 122 SibValueInfo(unsigned Reg, VNInfo *VNI) in SibValueInfo()
124 SpillReg(Reg), SpillVNI(VNI), SpillMBB(nullptr), DefMI(nullptr) {} in SibValueInfo()
158 bool isRegToSpill(unsigned Reg) { in isRegToSpill() argument
160 RegsToSpill.end(), Reg) != RegsToSpill.end(); in isRegToSpill()
163 bool isSibling(unsigned Reg);
175 bool coalesceStackAccess(MachineInstr *MI, unsigned Reg);
181 void spillAroundUses(unsigned Reg);
213 static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) { in isFullCopyOf() argument
216 if (MI->getOperand(0).getReg() == Reg) in isFullCopyOf()
218 if (MI->getOperand(1).getReg() == Reg) in isFullCopyOf()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 37 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
95 return MO->Contents.Reg.Next; in getNextOperandForReg()
216 void verifyUseList(unsigned Reg) const;
248 inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const { in reg_operands() argument
249 return iterator_range<reg_iterator>(reg_begin(Reg), reg_end()); in reg_operands()
264 reg_instructions(unsigned Reg) const { in reg_instructions() argument
265 return iterator_range<reg_instr_iterator>(reg_instr_begin(Reg), in reg_instructions()
280 inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const { in reg_bundles() argument
281 return iterator_range<reg_bundle_iterator>(reg_bundle_begin(Reg), in reg_bundles()
301 reg_nodbg_operands(unsigned Reg) const { in reg_nodbg_operands() argument
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| D | LiveIntervalAnalysis.h | 110 LiveInterval &getInterval(unsigned Reg) { in getInterval() argument
111 if (hasInterval(Reg)) in getInterval()
112 return *VirtRegIntervals[Reg]; in getInterval()
114 return createAndComputeVirtRegInterval(Reg); in getInterval()
117 const LiveInterval &getInterval(unsigned Reg) const { in getInterval() argument
118 return const_cast<LiveIntervals*>(this)->getInterval(Reg); in getInterval()
121 bool hasInterval(unsigned Reg) const { in hasInterval() argument
122 return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg]; in hasInterval()
126 LiveInterval &createEmptyInterval(unsigned Reg) { in createEmptyInterval() argument
127 assert(!hasInterval(Reg) && "Interval already exists!"); in createEmptyInterval()
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| D | LiveVariables.h | 110 unsigned Reg,
153 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
158 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
159 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
165 MachineInstr *FindLastRefOrPartRef(unsigned Reg);
170 MachineInstr *FindLastPartialDef(unsigned Reg,
188 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
195 void replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
285 bool isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) { in isLiveIn() argument
286 return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI); in isLiveIn()
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| D | StackMaps.h | 138 unsigned Reg; member
140 Location() : LocType(Unprocessed), Size(0), Reg(0), Offset(0) {} in Location()
141 Location(LocationType LocType, unsigned Size, unsigned Reg, int64_t Offset) in Location()
142 : LocType(LocType), Size(Size), Reg(Reg), Offset(Offset) {} in Location()
146 unsigned short Reg; member
150 LiveOutReg() : Reg(0), RegNo(0), Size(0) {} in LiveOutReg()
151 LiveOutReg(unsigned short Reg, unsigned short RegNo, unsigned short Size) in LiveOutReg()
152 : Reg(Reg), RegNo(RegNo), Size(Size) {} in LiveOutReg()
154 void MarkInvalid() { Reg = 0; } in MarkInvalid()
158 static bool IsInvalid(const LiveOutReg &LO) { return LO.Reg == 0; } in IsInvalid()
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| /external/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 66 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
90 unsigned Reg = MI->getOperand(1).getReg(); in getAccDefMI() local
91 if (TargetRegisterInfo::isPhysicalRegister(Reg)) in getAccDefMI()
95 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
100 Reg = DefMI->getOperand(1).getReg(); in getAccDefMI()
101 if (TargetRegisterInfo::isVirtualRegister(Reg)) { in getAccDefMI()
102 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
106 Reg = DefMI->getOperand(2).getReg(); in getAccDefMI()
107 if (TargetRegisterInfo::isVirtualRegister(Reg)) { in getAccDefMI()
108 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
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| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 109 RegOp Reg; member
144 Op->Reg.Kind = Kind; in createReg()
145 Op->Reg.Num = Num; in createReg()
195 return Kind == KindReg && Reg.Kind == RegKind; in isReg()
199 return Reg.Num; in getReg()
340 bool parseRegister(Register &Reg);
342 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
455 bool SystemZAsmParser::parseRegister(Register &Reg) { in parseRegister() argument
456 Reg.StartLoc = Parser.getTok().getLoc(); in parseRegister()
465 return Error(Reg.StartLoc, "invalid register"); in parseRegister()
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 67 bool contains(unsigned Reg) const { in contains() argument
68 unsigned InByte = Reg % 8; in contains()
69 unsigned Byte = Reg / 8; in contains()
338 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
342 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
456 MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
458 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
473 MCSubRegIndexIterator(unsigned Reg, const MCRegisterInfo *MCRI) in MCSubRegIndexIterator() argument
474 : SRIter(Reg, MCRI) { in MCSubRegIndexIterator()
475 SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices; in MCSubRegIndexIterator()
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| /external/llvm/lib/Target/R600/ |
| D | SIFixSGPRCopies.cpp | 90 unsigned Reg,
94 unsigned Reg,
137 unsigned Reg, in inferRegClassFromUses() argument
141 = TargetRegisterInfo::isVirtualRegister(Reg) ? in inferRegClassFromUses()
142 MRI.getRegClass(Reg) : in inferRegClassFromUses()
143 TRI->getRegClass(Reg); in inferRegClassFromUses()
147 I = MRI.use_instr_begin(Reg), E = MRI.use_instr_end(); I != E; ++I) { in inferRegClassFromUses()
163 unsigned Reg, in inferRegClassFromDef() argument
165 if (!TargetRegisterInfo::isVirtualRegister(Reg)) { in inferRegClassFromDef()
166 const TargetRegisterClass *RC = TRI->getPhysRegClass(Reg); in inferRegClassFromDef()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 78 bool contains(unsigned Reg) const { in contains() argument
79 return MC->contains(Reg); in contains()
269 static bool isStackSlot(unsigned Reg) { in isStackSlot() argument
270 return int(Reg) >= (1 << 30); in isStackSlot()
275 static int stackSlot2Index(unsigned Reg) { in stackSlot2Index() argument
276 assert(isStackSlot(Reg) && "Not a stack slot"); in stackSlot2Index()
277 return int(Reg - (1u << 30)); in stackSlot2Index()
289 static bool isPhysicalRegister(unsigned Reg) { in isPhysicalRegister() argument
290 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); in isPhysicalRegister()
291 return int(Reg) > 0; in isPhysicalRegister()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZShortenInst.cpp | 78 unsigned Reg = MI.getOperand(0).getReg(); in shortenIIF() local
79 assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number"); in shortenIIF()
80 unsigned GPRs = GPRMap[Reg]; in shortenIIF()
88 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg)); in shortenIIF()
93 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg)); in shortenIIF()
110 unsigned Reg = *LI; in processBlock() local
111 assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number"); in processBlock()
112 LiveLow |= LowGPRs[Reg]; in processBlock()
113 LiveHigh |= HighGPRs[Reg]; in processBlock()
133 if (unsigned Reg = MO.getReg()) { in processBlock() local
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| D | SystemZFrameLowering.cpp | 55 RegSpillOffsets[SpillOffsetTable[I].Reg] = SpillOffsetTable[I].Offset; in SystemZFrameLowering()
98 unsigned Reg = CSRegs[I]; in processFunctionBeforeCalleeSavedScan() local
99 if (SystemZ::GR64BitRegClass.contains(Reg) && MRI.isPhysRegUsed(Reg)) { in processFunctionBeforeCalleeSavedScan()
142 unsigned Reg = CSI[I].getReg(); in spillCalleeSavedRegisters() local
143 if (SystemZ::GR64BitRegClass.contains(Reg)) { in spillCalleeSavedRegisters()
144 unsigned Offset = RegSpillOffsets[Reg]; in spillCalleeSavedRegisters()
147 LowGPR = Reg; in spillCalleeSavedRegisters()
163 unsigned Reg = SystemZ::ArgGPRs[FirstGPR]; in spillCalleeSavedRegisters() local
164 unsigned Offset = RegSpillOffsets[Reg]; in spillCalleeSavedRegisters()
166 LowGPR = Reg; StartOffset = Offset; in spillCalleeSavedRegisters()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.cpp | 64 unsigned Reg, unsigned FrameReg, int Offset ) { in InsertFPImmInst() argument
71 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg) in InsertFPImmInst()
78 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst()
84 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg) in InsertFPImmInst()
95 unsigned Reg, unsigned FrameReg, in InsertFPConstInst() argument
107 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) in InsertFPConstInst()
114 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPConstInst()
120 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg) in InsertFPConstInst()
131 unsigned Reg, int Offset) { in InsertSPImmInst() argument
141 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsOptimizePICCall.cpp | 82 bool isCallViaRegister(MachineInstr &MI, unsigned &Reg,
94 void incCntAndSetReg(ValueType Entry, unsigned Reg);
118 static MVT::SimpleValueType getRegTy(unsigned Reg, MachineFunction &MF) { in getRegTy() argument
119 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg); in getRegTy()
148 unsigned Reg = Ty == MVT::i32 ? Mips::GP : Mips::GP_64; in eraseGPOpnd() local
152 if (MO.isReg() && MO.getReg() == Reg) { in eraseGPOpnd()
214 unsigned Reg; in visitNode() local
218 if (!isCallViaRegister(*I, Reg, Entry)) in visitNode()
238 incCntAndSetReg(Entry, Reg); in visitNode()
246 bool OptimizePICCall::isCallViaRegister(MachineInstr &MI, unsigned &Reg, in isCallViaRegister() argument
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