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Searched refs:Reg1 (Results 1 – 25 of 26) sorted by relevance

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/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64AsmBackend.cpp374 unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding() local
391 Reg1 = getXRegFromWReg(Reg1); in generateCompactUnwindEncoding()
394 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
397 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
400 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
403 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
406 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
410 Reg1 = getDRegFromBReg(Reg1); in generateCompactUnwindEncoding()
417 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
420 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
[all …]
/external/llvm/include/llvm/MC/
DMCRegisterInfo.h76 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
77 return contains(Reg1) && contains(Reg2); in contains()
600 uint16_t Reg1; variable
602 MCRegUnitRootIterator() : Reg0(0), Reg1(0) {} in MCRegUnitRootIterator()
606 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; in MCRegUnitRootIterator()
622 Reg0 = Reg1;
623 Reg1 = 0;
/external/llvm/lib/Target/AArch64/
DAArch64FrameLowering.cpp738 unsigned Reg1 = CSI[idx].getReg(); in spillCalleeSavedRegisters() local
760 if (AArch64::GPR64RegClass.contains(Reg1)) { in spillCalleeSavedRegisters()
768 } else if (AArch64::FPR64RegClass.contains(Reg1)) { in spillCalleeSavedRegisters()
778 DEBUG(dbgs() << "CSR spill: (" << TRI->getName(Reg1) << ", " in spillCalleeSavedRegisters()
790 MBB.addLiveIn(Reg1); in spillCalleeSavedRegisters()
793 .addReg(Reg1, getPrologueDeath(MF, Reg1)) in spillCalleeSavedRegisters()
815 unsigned Reg1 = CSI[i].getReg(); in restoreCalleeSavedRegisters() local
833 if (AArch64::GPR64RegClass.contains(Reg1)) { in restoreCalleeSavedRegisters()
840 } else if (AArch64::FPR64RegClass.contains(Reg1)) { in restoreCalleeSavedRegisters()
849 DEBUG(dbgs() << "CSR restore: (" << TRI->getName(Reg1) << ", " in restoreCalleeSavedRegisters()
[all …]
/external/llvm/lib/Target/Mips/
DMipsAsmPrinter.h73 unsigned Reg1, unsigned Reg2);
76 unsigned Reg1, unsigned Reg2, unsigned Reg3);
79 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
DMipsAsmPrinter.cpp789 unsigned Opcode, unsigned Reg1, in EmitInstrRegReg() argument
798 unsigned Temp = Reg1; in EmitInstrRegReg()
799 Reg1 = Reg2; in EmitInstrRegReg()
803 I.addOperand(MCOperand::CreateReg(Reg1)); in EmitInstrRegReg()
809 unsigned Opcode, unsigned Reg1, in EmitInstrRegRegReg() argument
813 I.addOperand(MCOperand::CreateReg(Reg1)); in EmitInstrRegRegReg()
820 unsigned MovOpc, unsigned Reg1, in EmitMovFPIntPair() argument
824 unsigned temp = Reg1; in EmitMovFPIntPair()
825 Reg1 = Reg2; in EmitMovFPIntPair()
828 EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1); in EmitMovFPIntPair()
DMips16InstrInfo.cpp265 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig() argument
274 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1); in adjustStackPtrBig()
278 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1); in adjustStackPtrBig()
279 MIB3.addReg(Reg1); in adjustStackPtrBig()
283 MIB4.addReg(Reg1, RegState::Kill); in adjustStackPtrBig()
DMipsSEFrameLowering.cpp434 unsigned Reg1 = in emitPrologue() local
438 std::swap(Reg0, Reg1); in emitPrologue()
446 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); in emitPrologue()
451 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; in emitPrologue() local
454 std::swap(Reg0, Reg1); in emitPrologue()
462 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); in emitPrologue()
DMips16InstrInfo.h117 unsigned Reg1, unsigned Reg2) const;
/external/llvm/lib/Target/X86/
DX86InstrBuilder.h116 unsigned Reg1, bool isKill1, in addRegReg() argument
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp465 unsigned Reg1 = Reg; in lowerCRSpilling() local
470 .addReg(Reg1, RegState::Kill) in lowerCRSpilling()
510 unsigned Reg1 = Reg; in lowerCRRestore() local
516 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) in lowerCRRestore()
554 unsigned Reg1 = Reg; in lowerCRBitSpilling() local
559 .addReg(Reg1, RegState::Kill) in lowerCRBitSpilling()
DPPCInstrInfo.cpp256 unsigned Reg1 = MI->getOperand(1).getReg(); in commuteInstruction() local
265 if (Reg0 == Reg1) { in commuteInstruction()
285 .addReg(Reg1, getKillRegState(Reg1IsKill)) in commuteInstruction()
294 MI->getOperand(2).setReg(Reg1); in commuteInstruction()
/external/llvm/lib/CodeGen/
DAggressiveAntiDepBreaker.h100 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
DTargetInstrInfo.cpp138 unsigned Reg1 = MI->getOperand(Idx1).getReg(); in commuteInstruction() local
147 if (HasDef && Reg0 == Reg1 && in commuteInstruction()
155 Reg0 = Reg1; in commuteInstruction()
169 MI->getOperand(Idx2).setReg(Reg1); in commuteInstruction()
DAggressiveAntiDepBreaker.cpp79 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) in UnionGroups() argument
85 unsigned Group1 = GetGroup(Reg1); in UnionGroups()
DRegisterCoalescer.cpp1851 unsigned Reg1; in valuesIdentical() local
1852 std::tie(Orig1, Reg1) = Other.followCopyChain(Value1); in valuesIdentical()
1858 return Orig0->def == Orig1->def && Reg0 == Reg1; in valuesIdentical()
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp1471 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwo() local
1475 printRegName(O, Reg1); in printVectorListTwo()
1484 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpaced() local
1488 printRegName(O, Reg1); in printVectorListTwoSpaced()
1539 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwoAllLanes() local
1543 printRegName(O, Reg1); in printVectorListTwoAllLanes()
1586 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpacedAllLanes() local
1590 printRegName(O, Reg1); in printVectorListTwoSpacedAllLanes()
/external/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp89 unsigned Reg1, unsigned Reg2);
469 unsigned Reg1, unsigned Reg2) { in createRegSequence() argument
475 .addReg(Reg1) in createRegSequence()
DThumb2SizeReduction.cpp642 unsigned Reg1 = MI->getOperand(1).getReg(); in ReduceTo2Addr() local
647 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()
653 if (Reg1 != Reg0) in ReduceTo2Addr()
660 } else if (Reg0 != Reg1) { in ReduceTo2Addr()
DARMFastISel.cpp2781 unsigned Reg1 = getRegForValue(Src1Value); in SelectShift() local
2782 if (Reg1 == 0) return false; in SelectShift()
2795 .addReg(Reg1); in SelectShift()
DARMISelDAGToDAG.cpp3390 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); in SelectInlineAsm() local
3414 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in SelectInlineAsm()
3429 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32, in SelectInlineAsm()
DARMBaseInstrInfo.cpp2706 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); in FoldImmediate() local
2712 .addReg(Reg1, getKillRegState(isKill)) in FoldImmediate()
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h83 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
84 return MC->contains(Reg1, Reg2); in contains()
/external/llvm/utils/TableGen/
DCodeGenRegisters.cpp1122 for (const auto &Reg1 : Registers) { in computeComposites() local
1124 if (TopoSigs.test(Reg1.getTopoSig())) in computeComposites()
1126 TopoSigs.set(Reg1.getTopoSig()); in computeComposites()
1128 const CodeGenRegister::SubRegMap &SRM1 = Reg1.getSubRegs(); in computeComposites()
1134 if (&Reg1 == Reg2) in computeComposites()
1146 CodeGenSubRegIndex *Idx3 = Reg1.getSubRegIndex(Reg3); in computeComposites()
/external/llvm/lib/MC/
DMCDwarf.cpp1046 unsigned Reg1 = Instr.getRegister(); in EmitCFIInstruction() local
1049 Reg1 = MRI->getDwarfRegNum(MRI->getLLVMRegNum(Reg1, true), false); in EmitCFIInstruction()
1053 Streamer.EmitULEB128IntValue(Reg1); in EmitCFIInstruction()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp5884 unsigned Reg1 = Op1.getReg(); in ParseInstruction() local
5886 unsigned Rt = MRI->getEncodingValue(Reg1); in ParseInstruction()
5896 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0, in ParseInstruction()

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