/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
D | AArch64AsmBackend.cpp | 381 unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true); in generateCompactUnwindEncoding() local 392 Reg2 = getXRegFromWReg(Reg2); in generateCompactUnwindEncoding() 394 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding() 397 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding() 400 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding() 403 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding() 406 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding() 411 Reg2 = getDRegFromBReg(Reg2); in generateCompactUnwindEncoding() 417 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding() 420 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding() [all …]
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/external/llvm/lib/Target/AArch64/ |
D | AArch64FrameLowering.cpp | 739 unsigned Reg2 = CSI[idx + 1].getReg(); in spillCalleeSavedRegisters() local 761 assert(AArch64::GPR64RegClass.contains(Reg2) && in spillCalleeSavedRegisters() 769 assert(AArch64::FPR64RegClass.contains(Reg2) && in spillCalleeSavedRegisters() 779 << TRI->getName(Reg2) << ") -> fi#(" << CSI[idx].getFrameIdx() in spillCalleeSavedRegisters() 791 MBB.addLiveIn(Reg2); in spillCalleeSavedRegisters() 792 MIB.addReg(Reg2, getPrologueDeath(MF, Reg2)) in spillCalleeSavedRegisters() 816 unsigned Reg2 = CSI[i + 1].getReg(); in restoreCalleeSavedRegisters() local 834 assert(AArch64::GPR64RegClass.contains(Reg2) && in restoreCalleeSavedRegisters() 841 assert(AArch64::FPR64RegClass.contains(Reg2) && in restoreCalleeSavedRegisters() 850 << TRI->getName(Reg2) << ") -> fi#(" << CSI[i].getFrameIdx() in restoreCalleeSavedRegisters() [all …]
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/external/llvm/lib/Target/Mips/ |
D | MipsAsmPrinter.h | 73 unsigned Reg1, unsigned Reg2); 76 unsigned Reg1, unsigned Reg2, unsigned Reg3); 79 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
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D | MipsAsmPrinter.cpp | 790 unsigned Reg2) { in EmitInstrRegReg() argument 799 Reg1 = Reg2; in EmitInstrRegReg() 800 Reg2 = Temp; in EmitInstrRegReg() 804 I.addOperand(MCOperand::CreateReg(Reg2)); in EmitInstrRegReg() 810 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg() argument 814 I.addOperand(MCOperand::CreateReg(Reg2)); in EmitInstrRegRegReg() 821 unsigned Reg2, unsigned FPReg1, in EmitMovFPIntPair() argument 825 Reg1 = Reg2; in EmitMovFPIntPair() 826 Reg2 = temp; in EmitMovFPIntPair() 829 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2); in EmitMovFPIntPair()
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D | Mips16InstrInfo.h | 117 unsigned Reg1, unsigned Reg2) const;
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D | Mips16InstrInfo.cpp | 265 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig() 276 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2); in adjustStackPtrBig() 280 MIB3.addReg(Reg2, RegState::Kill); in adjustStackPtrBig()
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D | MipsISelLowering.cpp | 2394 unsigned Reg2 = State.AllocateReg(IntRegs); in CC_MipsO32() local 2395 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) in CC_MipsO32() 2969 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), in LowerFormalArguments() local 2971 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); in LowerFormalArguments()
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/external/llvm/test/CodeGen/Hexagon/ |
D | newvaluejump2.ll | 9 %Reg2 = alloca i8, align 1 10 %0 = load i8, i8* %Reg2, align 1
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/external/llvm/lib/Target/X86/ |
D | X86InstrBuilder.h | 117 unsigned Reg2, bool isKill2) { in addRegReg() argument 119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
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D | X86InstrInfo.cpp | 4876 unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg(); in foldMemoryOperandImpl() local 4885 (HasDef && Reg0 == Reg2 && Tied1)) in foldMemoryOperandImpl()
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/external/llvm/lib/Target/ARM/ |
D | Thumb2SizeReduction.cpp | 645 unsigned Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local 648 || !isARMLowRegister(Reg2)) in ReduceTo2Addr() 650 if (Reg0 != Reg2) { in ReduceTo2Addr() 678 unsigned Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local 679 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) in ReduceTo2Addr()
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D | A15SDOptimizer.cpp | 89 unsigned Reg1, unsigned Reg2); 469 unsigned Reg1, unsigned Reg2) { in createRegSequence() argument 477 .addReg(Reg2) in createRegSequence()
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D | ARMFastISel.cpp | 2784 unsigned Reg2 = 0; in SelectShift() local 2786 Reg2 = getRegForValue(Src2Value); in SelectShift() 2787 if (Reg2 == 0) return false; in SelectShift() 2800 MIB.addReg(Reg2); in SelectShift()
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/external/llvm/lib/CodeGen/ |
D | AggressiveAntiDepBreaker.h | 100 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
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D | TargetInstrInfo.cpp | 139 unsigned Reg2 = MI->getOperand(Idx2).getReg(); in commuteInstruction() local 150 Reg0 = Reg2; in commuteInstruction() 152 } else if (HasDef && Reg0 == Reg2 && in commuteInstruction() 170 MI->getOperand(Idx1).setReg(Reg2); in commuteInstruction()
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D | AggressiveAntiDepBreaker.cpp | 79 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) in UnionGroups() argument 86 unsigned Group2 = GetGroup(Reg2); in UnionGroups()
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/external/llvm/include/llvm/MC/ |
D | MCRegisterInfo.h | 76 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument 77 return contains(Reg1) && contains(Reg2); in contains()
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/external/llvm/include/llvm/Target/ |
D | TargetRegisterInfo.h | 83 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument 84 return MC->contains(Reg1, Reg2); in contains()
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/external/llvm/lib/MC/ |
D | MCDwarf.cpp | 1047 unsigned Reg2 = Instr.getRegister2(); in EmitCFIInstruction() local 1050 Reg2 = MRI->getDwarfRegNum(MRI->getLLVMRegNum(Reg2, true), false); in EmitCFIInstruction() 1054 Streamer.EmitULEB128IntValue(Reg2); in EmitCFIInstruction()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCInstrInfo.cpp | 257 unsigned Reg2 = MI->getOperand(2).getReg(); in commuteInstruction() local 280 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); in commuteInstruction() 284 .addReg(Reg2, getKillRegState(Reg2IsKill)) in commuteInstruction() 291 MI->getOperand(0).setReg(Reg2); in commuteInstruction() 295 MI->getOperand(1).setReg(Reg2); in commuteInstruction()
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/external/llvm/utils/TableGen/ |
D | CodeGenRegisters.cpp | 1132 CodeGenRegister *Reg2 = i1->second; in computeComposites() local 1134 if (&Reg1 == Reg2) in computeComposites() 1136 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); in computeComposites() 1143 if (Reg2 == Reg3) in computeComposites()
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/external/llvm/lib/Target/ARM/AsmParser/ |
D | ARMAsmParser.cpp | 5885 unsigned Reg2 = Op2.getReg(); in ParseInstruction() local 5887 unsigned Rt2 = MRI->getEncodingValue(Reg2); in ParseInstruction()
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