| /external/llvm/lib/Target/BPF/InstPrinter/ |
| D | BPFInstPrinter.cpp | 66 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemOperand() local
75 assert(RegOp.isReg() && "Register operand not a register"); in printMemOperand()
76 O << '(' << getRegisterName(RegOp.getReg()) << ')'; in printMemOperand()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 493 unsigned RegOp = OpNum; in PrintAsmOperand() local
499 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum; in PrintAsmOperand()
502 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1; in PrintAsmOperand()
505 RegOp = OpNum + 1; in PrintAsmOperand()
507 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
509 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /external/llvm/lib/Target/R600/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 79 struct RegOp { struct in __anon92a627a80111::AMDGPUOperand
88 RegOp Reg;
643 AMDGPUOperand &RegOp = ((AMDGPUOperand&)*Operands[PrevRegIdx]); in parseOperand() local
644 RegOp.setModifiers(0); in parseOperand()
653 AMDGPUOperand &RegOp = ((AMDGPUOperand&)*Operands[Operands.size() - 1]); in parseOperand() local
654 RegOp.setModifiers(Modifiers); in parseOperand()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 1712 const MCOperand &RegOp = Inst.getOperand(0); in expandLoadImm() local
1713 assert(RegOp.isReg() && "expected register operand kind"); in expandLoadImm()
1723 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg())); in expandLoadImm()
1731 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg())); in expandLoadImm()
1740 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg())); in expandLoadImm()
1743 createShiftOr<0, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions); in expandLoadImm()
1764 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg())); in expandLoadImm()
1768 createShiftOr<16, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions); in expandLoadImm()
1769 createShiftOr<0, true>(ImmValue, RegOp.getReg(), IDLoc, Instructions); in expandLoadImm()
1791 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg())); in expandLoadImm()
[all …]
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| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfCompileUnit.cpp | 493 const MachineOperand RegOp = DVInsn->getOperand(0); in constructVariableDIEImpl() local
496 MachineLocation Location(RegOp.getReg(), in constructVariableDIEImpl()
499 } else if (RegOp.getReg()) in constructVariableDIEImpl()
500 addVariableAddress(DV, *VariableDie, MachineLocation(RegOp.getReg())); in constructVariableDIEImpl()
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86Operand.h | 41 struct RegOp { struct
61 struct RegOp Reg;
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 95 uint16_t RegOp; member
273 unsigned RegOp = MemoryFoldTable2Addr[i].RegOp; in X86InstrInfo() local
277 RegOp, MemOp, in X86InstrInfo()
428 unsigned RegOp = MemoryFoldTable0[i].RegOp; in X86InstrInfo() local
432 RegOp, MemOp, TB_INDEX_0 | Flags); in X86InstrInfo()
864 unsigned RegOp = MemoryFoldTable1[i].RegOp; in X86InstrInfo() local
868 RegOp, MemOp, in X86InstrInfo()
1731 unsigned RegOp = MemoryFoldTable2[i].RegOp; in X86InstrInfo() local
1735 RegOp, MemOp, in X86InstrInfo()
1947 unsigned RegOp = MemoryFoldTable3[i].RegOp; in X86InstrInfo() local
[all …]
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| D | X86InstrInfo.h | 165 unsigned RegOp, unsigned MemOp, unsigned Flags);
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| D | X86MCInstLower.cpp | 351 unsigned RegOp = IsStore ? 0 : 5; in SimplifyShortMoveForm() local
353 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && in SimplifyShortMoveForm()
363 unsigned Reg = Inst.getOperand(RegOp).getReg(); in SimplifyShortMoveForm()
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| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 82 struct RegOp { struct in __anon765a2c600111::SystemZOperand
109 RegOp Reg;
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| /external/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 157 struct RegOp { struct in __anon818a29540111::SparcOperand
174 struct RegOp Reg;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 349 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1; in PrintAsmOperand() local
350 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
352 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 172 struct RegOp { struct in __anon0b51bef40211::AArch64Operand
241 struct RegOp Reg;
3815 AArch64Operand &RegOp = static_cast<AArch64Operand &>(*Operands[1]); in MatchAndEmitInstruction() local
3817 if (RegOp.isReg() && ImmOp.isFPImm() && ImmOp.getFPImm() == (unsigned)-1) { in MatchAndEmitInstruction()
3820 RegOp.getReg()) in MatchAndEmitInstruction()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 464 struct RegOp { struct in __anon0735be620311::ARMOperand
548 struct RegOp Reg;
4701 unsigned RegOp = 4; in cvtThumbMultiply() local
4705 RegOp = 5; in cvtThumbMultiply()
4706 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1); in cvtThumbMultiply()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfoV4.td | 1549 bits<5> RegOp; // Non-New-Value Operand
1557 let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
1565 let Inst{12-8} = RegOp;
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