| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 783 SETOGT, // 0 0 1 0 True if ordered and greater than enumerator
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| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 165 case FCmpInst::FCMP_OGT: return ISD::SETOGT; in getFCmpCondCode()
189 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT; in getFCmpCodeWithoutNaN()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstructions.td | 52 case ISD::SETOGT: case ISD::SETUGT:
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| D | AMDILISelLowering.cpp | 133 setOperationAction(ISD::SETOGT, VT, Expand); in InitAMDILLowering()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 306 case ISD::SETOGT: return "setogt"; in getOperationName()
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| D | TargetLowering.cpp | 156 case ISD::SETOGT: in softenSetCCOperands()
1786 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); in SimplifySetCC()
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| D | SelectionDAG.cpp | 360 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE in getSetCCAndOperation()
1849 case ISD::SETOGT: in FoldSetCC()
1903 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); in FoldSetCC()
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| D | LegalizeDAG.cpp | 1709 case ISD::SETOGT: in LegalizeSetCCCondCode()
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| D | DAGCombiner.cpp | 4732 case ISD::SETOGT: in combineMinNumMaxNum()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 2045 case ISD::SETOGT: in getPredicateForSetCC()
2066 case ISD::SETOGT: in getCRIdxForSetCC()
2103 case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break; in getVCmpInst()
2112 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break; in getVCmpInst()
2126 case ISD::SETOGT: in getVCmpInst()
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| D | PPCInstrQPX.td | 473 (setcc v4f64:$FRA, v4f64:$FRB, SETOGT))]>;
478 (setcc v4f32:$FRA, v4f32:$FRB, SETOGT))]>;
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| D | PPCInstrInfo.td | 3098 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
3129 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1438 setCondCodeAction(ISD::SETOGT, MVT::f32, Legal); in HexagonTargetLowering()
1439 setCondCodeAction(ISD::SETOGT, MVT::f64, Legal); in HexagonTargetLowering()
1536 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand); in HexagonTargetLowering()
1539 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUInstructions.td | 81 [{return N->get() == ISD::SETOGT || N->get() == ISD::SETGT;}]
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| D | AMDGPUISelLowering.cpp | 1132 case ISD::SETOGT: { in CombineFMinMaxLegacy()
1923 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT); in LowerFCEIL()
2013 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT); in LowerFRINT()
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| D | SIISelLowering.cpp | 1106 SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT); in LowerFDIV32()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 538 def SETOEQ : CondCode; def SETOGT : CondCode;
877 (setcc node:$lhs, node:$rhs, SETOGT)>;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 192 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand); in MipsSETargetLowering()
197 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand); in MipsSETargetLowering()
324 setCondCodeAction(ISD::SETOGT, Ty, Expand); in addMSAFloatType()
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| D | MipsMSAInstrInfo.td | 173 def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>;
174 def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>;
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| D | MipsISelLowering.cpp | 497 case ISD::SETOGT: return Mips::FCOND_OGT; in condCodeToFCC()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXVector.td | 954 (setcc node:$lhs, node:$rhs, SETOGT)>;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1242 case ISD::SETOGT: CondCode = ARMCC::GT; break; in FPCCToARMCC()
3390 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT || in checkVSELConstraints()
4369 case ISD::SETOGT: in LowerVSETCC()
9702 case ISD::SETOGT: in PerformSELECT_CCCombine()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1353 case ISD::SETOGT: return SPCC::FCC_G; in FPCondCCodeToFCC()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1034 case ISD::SETOGT: in changeFPCCToAArch64CC()
3712 case ISD::SETOGT: in LowerSELECT_CC()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 3699 case ISD::SETOGT: in TranslateX86CC()
12932 case ISD::SETOGT: in translateX86FSETCC()
20847 case ISD::SETOGT: in PerformSELECTCombine()
20881 case ISD::SETOGT: in PerformSELECTCombine()
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