Home
last modified time | relevance | path

Searched refs:SSE1 (Results 1 – 15 of 15) sorted by relevance

/external/llvm/test/CodeGen/X86/
Dvector-shuffle-sse1.ll1 ; RUN: llc < %s -mcpu=x86-64 -mattr=-sse2 | FileCheck %s --check-prefix=SSE1
6 ; SSE1-LABEL: shuffle_v4f32_0001:
7 ; SSE1: # BB#0:
8 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,1]
9 ; SSE1-NEXT: retq
14 ; SSE1-LABEL: shuffle_v4f32_0020:
15 ; SSE1: # BB#0:
16 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,2,0]
17 ; SSE1-NEXT: retq
22 ; SSE1-LABEL: shuffle_v4f32_0300:
[all …]
Dmemcpy-2.ll3 …llc < %s -mattr=+sse,-sse2 -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSE1
26 ; SSE1-LABEL: t1:
27 ; SSE1: movaps _.str, %xmm0
28 ; SSE1: movaps %xmm0
29 ; SSE1: movb $0, 24(%esp)
30 ; SSE1: movl $0, 20(%esp)
31 ; SSE1: movl $0, 16(%esp)
66 ; SSE1-LABEL: t2:
67 ; SSE1: movaps (%ecx), %xmm0
68 ; SSE1: movaps %xmm0, (%eax)
[all …]
Dmemset-sse-stack-realignment.ll5 ; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=pentium3 | FileCheck %s -check-prefix=SSE1
21 ; SSE1-LABEL: test1:
22 ; SSE1: andl $-16
23 ; SSE1: movl %esp, %esi
24 ; SSE1: movaps
54 ; SSE1-LABEL: test2:
55 ; SSE1: andl $-16
56 ; SSE1: movl %esp, %esi
57 ; SSE1: movaps
Dsse1.ll1 ; Tests for SSE1 and below, without SSE2+.
37 ; vselect. With SSE1 v4f32 is a legal type but v4i1 (or any vector integer type)
/external/llvm/lib/Target/X86/
DX86Subtarget.h50 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F enumerator
328 bool hasSSE1() const { return X86SSELevel >= SSE1; } in hasSSE1()
DX86InstrFormats.td498 // SSE1 Instruction Templates:
500 // SSI - SSE1 instructions with XS prefix.
501 // PSI - SSE1 instructions with PS prefix.
502 // PSIi8 - SSE1 instructions with ImmT == Imm8 and PS prefix.
503 // VSSI - SSE1 instructions with XS prefix in AVX form.
504 // VPSI - SSE1 instructions with PS prefix in AVX form, packed single.
DX86.td43 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
46 // SSE1+ processors support them.
DX86InstrFPStack.td118 // f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1.
DX86InstrSSE.td579 // SSE1 & 2
2959 // SSE1, but only on SSE2.
3341 /// sse_fp_unop_s - SSE1 unops in scalar form
3443 /// sse1_fp_unop_p - SSE1 unops in packed form.
3479 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
DX86InstrCompiler.td501 // SSE1/SSE2.
/external/clang/lib/Basic/
DTargets.cpp1929 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F enumerator
2588 case SSE1: in setSSELevel()
2598 case SSE1: in setSSELevel()
2687 setSSELevel(Features, SSE1, Enabled); in setFeatureEnabledImpl()
2873 .Case("sse", SSE1) in handleTargetFeatures()
2911 if (FPMath == FP_SSE && SSELevel < SSE1) { in handleTargetFeatures()
2914 } else if (FPMath == FP_387 && SSELevel >= SSE1) { in handleTargetFeatures()
3200 case SSE1: in getTargetDefines()
3219 case SSE1: in getTargetDefines()
3278 .Case("sse", SSELevel >= SSE1) in hasFeature()
/external/valgrind/docs/internals/
D3_0_BUGSTATUS.txt426 110274 SSE1 now mandatory for x86
/external/llvm/include/llvm/IR/
DIntrinsicsX86.td113 // SSE1
/external/valgrind/
DNEWS.old897 110274 SSE1 now mandatory for x86
/external/libvncserver/x11vnc/misc/enhanced_tightvnc_viewer/src/patches/
Dtight-vncviewer-full.patch17612 +#define TJ_FORCESSE 16 /* Force IPP to use SSE1 code even if SSE2 available */