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Searched refs:SetCC (Results 1 – 25 of 29) sorted by relevance

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/external/v8/test/cctest/
Dtest-disasm-arm.cc107 COMPARE(and_(r2, r3, Operand(r4), SetCC), in TEST()
114 COMPARE(eor(r4, r5, Operand(r7, LSL, 1), SetCC), in TEST()
118 COMPARE(eor(r4, r5, Operand(r9, LSL, 3), SetCC, cs), in TEST()
123 COMPARE(sub(r5, r6, Operand(r10, LSL, 30), SetCC, cc), in TEST()
127 COMPARE(sub(r5, r6, Operand(r10, LSL, 16), SetCC, mi), in TEST()
134 COMPARE(rsb(r6, r7, Operand(fp, LSR, 0), SetCC), in TEST()
143 COMPARE(add(r7, r8, Operand(ip), SetCC), in TEST()
145 COMPARE(add(r7, r8, Operand(ip, ASR, 31), SetCC, vs), in TEST()
152 COMPARE(adc(r5, sp, Operand(ip), SetCC), in TEST()
154 COMPARE(adc(r8, lr, Operand(ip, ASR, 31), SetCC, vc), in TEST()
[all …]
Dtest-assembler-arm.cc951 __ mov(r1, Operand(r1, ASR, 1), SetCC);
956 __ mov(r2, Operand(r2, ASR, 1), SetCC);
963 __ mov(r3, Operand(r1, ASR, 1), SetCC); // Set the carry.
969 __ mov(r3, Operand(r2, ASR, 1), SetCC); // Unset the carry.
/external/llvm/test/CodeGen/AArch64/
Dsetcc-takes-i32.ll4 ; correctly. Previously LLVM thought that i64 was the appropriate SetCC output,
8 ; It was expecting the smallest legal promotion of i1 to be the preferred SetCC
/external/llvm/lib/Target/X86/
DX86InstrCMovSetCC.td1 //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
16 // SetCC instructions.
82 // SetCC instructions.
DX86ISelLowering.cpp13341 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, in LowerSETCC() local
13345 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC); in LowerSETCC()
13346 return SetCC; in LowerSETCC()
13364 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, in LowerSETCC() local
13367 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC); in LowerSETCC()
13368 return SetCC; in LowerSETCC()
14841 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, in LowerINTRINSIC_WO_CHAIN() local
14843 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); in LowerINTRINSIC_WO_CHAIN()
14975 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); in LowerINTRINSIC_WO_CHAIN() local
14976 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); in LowerINTRINSIC_WO_CHAIN()
[all …]
/external/llvm/test/Transforms/ConstProp/
D2002-09-03-SetCC-Bools.ll1 ; SetCC on boolean values was not implemented!
/external/v8/src/compiler/arm/
Dcode-generator-arm.cc34 return SetCC; in OutputSBit()
260 DCHECK_EQ(SetCC, i.OutputSBit()); in AssembleArchInstruction()
264 DCHECK_EQ(SetCC, i.OutputSBit()); in AssembleArchInstruction()
268 DCHECK_EQ(SetCC, i.OutputSBit()); in AssembleArchInstruction()
272 DCHECK_EQ(SetCC, i.OutputSBit()); in AssembleArchInstruction()
277 DCHECK_EQ(SetCC, i.OutputSBit()); in AssembleArchInstruction()
/external/v8/src/arm/
Dcodegen-arm.cc139 __ sub(chars, chars, Operand(64), SetCC); in CreateMemCopyUint8Function()
198 __ bic(temp1, chars, Operand(0x3), SetCC); in CreateMemCopyUint8Function()
206 __ bic(temp2, chars, Operand(0x3), SetCC); in CreateMemCopyUint8Function()
218 __ mov(chars, Operand(chars, LSL, 31), SetCC); in CreateMemCopyUint8Function()
301 __ mov(chars, Operand(chars, LSL, 31), SetCC); // bit0 => ne, bit1 => cs in CreateMemCopyUint16Uint8Function()
Dregexp-macro-assembler-arm.cc231 __ sub(r1, r1, r0, SetCC); // Length of capture. in CheckNotBackReferenceIgnoreCase()
342 __ sub(r1, r1, r0, SetCC); // Length to check. in CheckNotBackReference()
618 __ sub(r0, sp, r0, SetCC); in GetCode()
681 __ sub(r2, r2, Operand(1), SetCC); in GetCode()
Dlithium-codegen-arm.cc873 __ sub(r1, r1, Operand(1), SetCC); in DeoptimizeIf()
1159 __ rsb(dividend, dividend, Operand::Zero(), SetCC); in DoModByPowerOf2I()
1186 __ sub(result, dividend, result, SetCC); in DoModByConstI()
1295 __ sub(result_reg, left_reg, scratch, SetCC); in DoModI()
1376 __ sub(scratch0(), scratch0(), dividend, SetCC); in DoDivByConstI()
1488 __ rsb(result, dividend, Operand::Zero(), SetCC); in DoFlooringDivByPowerOf2I()
1644 __ rsb(result, left, Operand::Zero(), SetCC); in DoMulI()
1783 __ mov(result, Operand(left, LSR, scratch), SetCC); in DoShiftI()
1832 __ SmiTag(result, result, SetCC); in DoShiftI()
1834 __ SmiTag(result, left, SetCC); in DoShiftI()
[all …]
Dmacro-assembler-arm.cc1790 and_(scratch2, result, Operand(kDoubleAlignmentMask), SetCC); in Allocate()
1818 add(scratch2, source, bits_operand, SetCC, cond); in Allocate()
1904 and_(scratch2, result, Operand(kDoubleAlignmentMask), SetCC); in Allocate()
1920 add(scratch2, result, Operand(object_size, LSL, kPointerSizeLog2), SetCC); in Allocate()
1922 add(scratch2, result, Operand(object_size), SetCC); in Allocate()
2565 sub(result, result, Operand(1), SetCC); in TryInt32Floor()
2958 sub(scratch, reg, Operand(1), SetCC); in JumpIfNotPowerOfTwoOrZero()
2970 sub(scratch, reg, Operand(1), SetCC); in JumpIfNotPowerOfTwoOrZeroAndNeg()
2990 SmiUntag(dst, src, SetCC); in UntagAndJumpIfSmi()
2998 SmiUntag(dst, src, SetCC); in UntagAndJumpIfNotSmi()
[all …]
Dcode-stubs-arm.cc193 __ rsb(scratch, scratch, Operand(51), SetCC); in Generate()
370 __ orr(r0, r3, Operand(r2), SetCC); in EmitIdenticalObjectComparison()
908 __ mov(scratch, Operand(scratch, ASR, 1), SetCC); in Generate()
1841 __ SmiUntag(r1, SetCC); in GenerateNewStrict()
2022 SetCC); in Generate()
2069 __ mov(r3, Operand(r0, ASR, 2), SetCC); in Generate()
2275 __ sub(r1, r1, Operand(1), SetCC); in Generate()
2904 __ add(count, count, Operand(count), SetCC); in GenerateCopyCharacters()
2952 __ mov(r2, Operand(r2, ROR, 1), SetCC); in Generate()
2953 __ mov(r3, Operand(r3, ROR, 1), SetCC, cc); in Generate()
[all …]
Dconstants-arm.h215 SetCC = 1 << 20, // Set condition code. enumerator
Dfull-codegen-arm.cc179 __ sub(r2, r2, Operand(1), SetCC); in Generate()
345 __ sub(r3, r3, Operand(Smi::FromInt(delta)), SetCC); in EmitProfilingCounterDecrement()
1247 __ mov(r3, Operand(r0), SetCC); in VisitForInStatement()
2191 __ sub(r3, r3, Operand(Smi::FromInt(1)), SetCC); in EmitGeneratorResume()
2246 __ sub(r3, r3, Operand(1), SetCC); in EmitGeneratorResume()
2415 __ add(scratch1, left, Operand(right), SetCC); in EmitInlineSmiBinaryOp()
2420 __ sub(scratch1, left, Operand(right), SetCC); in EmitInlineSmiBinaryOp()
2433 __ add(scratch2, right, Operand(left), SetCC); in EmitInlineSmiBinaryOp()
3948 __ SmiUntag(array_length, SetCC); in EmitFastOneByteArrayJoin()
3985 __ add(string_length, string_length, Operand(scratch), SetCC); in EmitFastOneByteArrayJoin()
[all …]
Dbuiltins-arm.cc496 __ sub(r3, r3, Operand(r6), SetCC); in Generate_JSConstructStubHelper()
645 __ sub(r3, r3, Operand(2), SetCC); in Generate_JSConstructStubHelper()
Dmacro-assembler-arm.h1234 SmiTag(ip, src, SetCC); in TrySmiTag()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp567 SDValue SetCC = N->getOperand(0); in performSELECTCombine() local
569 if ((SetCC.getOpcode() != ISD::SETCC) || in performSELECTCombine()
570 !SetCC.getOperand(0).getValueType().isInteger()) in performSELECTCombine()
594 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
597 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
598 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); in performSELECTCombine()
600 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); in performSELECTCombine()
623 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); in performSELECTCombine()
630 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
631 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
[all …]
DMipsSEISelLowering.cpp1025 SDValue SetCC = N->getOperand(0); in performVSELECTCombine() local
1027 if (SetCC.getOpcode() != MipsISD::SETCC_DSP) in performVSELECTCombine()
1031 SetCC.getOperand(0), SetCC.getOperand(1), in performVSELECTCombine()
1032 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); in performVSELECTCombine()
/external/v8/src/x64/
Ddisasm-x64.cc413 int SetCC(byte* data);
807 int DisassemblerX64::SetCC(byte* data) { in SetCC() function in disasm::DisassemblerX64
1294 current = data + SetCC(data); in TwoByteOpcodeInstruction()
/external/v8/src/x87/
Ddisasm-x87.cc338 int SetCC(byte* data);
662 int DisassemblerX87::SetCC(byte* data) { in SetCC() function in disasm::DisassemblerX87
1121 data += SetCC(data); in InstructionDecode()
/external/v8/src/ia32/
Ddisasm-ia32.cc338 int SetCC(byte* data);
662 int DisassemblerIA32::SetCC(byte* data) { in SetCC() function in disasm::DisassemblerIA32
1100 data += SetCC(data); in InstructionDecode()
/external/llvm/lib/Target/R600/
DSIISelLowering.cpp749 SDNode *SetCC = Intr; in LowerBRCOND() local
750 assert(SetCC->getConstantOperandVal(1) == 1); in LowerBRCOND()
751 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == in LowerBRCOND()
753 Intr = SetCC->getOperand(0).getNode(); in LowerBRCOND()
/external/llvm/test/CodeGen/Generic/
Dselect.ll22 ; A SetCC whose result is used should produce instructions to
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp5419 SDNode *SetCC = SetCCs[i]; in ExtendSetCCUses() local
5423 SDValue SOp = SetCC->getOperand(j); in ExtendSetCCUses()
5430 Ops.push_back(SetCC->getOperand(2)); in ExtendSetCCUses()
5431 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops)); in ExtendSetCCUses()
5736 SDValue SetCC = DAG.getSetCC(DL, SetCCVT, in visitSIGN_EXTEND() local
5738 return DAG.getSelect(DL, VT, SetCC, in visitSIGN_EXTEND()
8439 SDValue SetCC = in visitBRCOND() local
8446 MVT::Other, Chain, SetCC, N2); in visitBRCOND()
8455 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); in visitBRCOND()
8508 SDValue SetCC = DAG.getSetCC(SDLoc(TheXor), in visitBRCOND() local
[all …]
/external/v8/src/ic/arm/
Dic-arm.cc544 __ sub(r5, r5, r6, SetCC); in GenerateGeneric()

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