Searched refs:SrcMO (Results 1 – 3 of 3) sorted by relevance
92 MachineOperand &SrcMO = MI->getOperand(1); in processBlock() local95 !IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()100 IsVRReg(SrcMO.getReg(), MRI) ? &PPC::VSHRCRegClass : in processBlock()102 assert((IsF8Reg(SrcMO.getReg(), MRI) || in processBlock()103 IsVRReg(SrcMO.getReg(), MRI)) && in processBlock()111 .addOperand(SrcMO) in processBlock()112 .addImm(IsVRReg(SrcMO.getReg(), MRI) ? PPC::sub_128 : in processBlock()116 SrcMO.setReg(NewVReg); in processBlock()118 IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()133 .addOperand(SrcMO); in processBlock()[all …]
147 MachineOperand &SrcMO = MI->getOperand(1); in LowerCopy() local149 if (SrcMO.getReg() == DstMO.getReg()) { in LowerCopy()153 if (SrcMO.isUndef() || MI->getNumOperands() > 2) { in LowerCopy()167 DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill()); in LowerCopy()
1381 MachineOperand &SrcMO = MI->getOperand(SrcIdx); in collectTiedOperands() local1383 unsigned SrcReg = SrcMO.getReg(); in collectTiedOperands()1389 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid"); in collectTiedOperands()1392 if (SrcMO.isUndef() && !DstMO.getSubReg()) { in collectTiedOperands()1398 SrcMO.setReg(DstReg); in collectTiedOperands()1399 SrcMO.setSubReg(0); in collectTiedOperands()