/external/harfbuzz_ng/src/ |
D | hb-ot-shape-complex-indic-table.cc | 94 /* 0900 */ _(Bi,x), _(Bi,x), _(Bi,x), _(Vs,x), _(VI,x), _(VI,x), _(VI,x), _(VI,x), 95 /* 0908 */ _(VI,x), _(VI,x), _(VI,x), _(VI,x), _(VI,x), _(VI,x), _(VI,x), _(VI,x), 96 /* 0910 */ _(VI,x), _(VI,x), _(VI,x), _(VI,x), _(VI,x), _(C,x), _(C,x), _(C,x), 106 /* 0960 */ _(VI,x), _(VI,x), _(M,B), _(M,B), _(x,x), _(x,x), _(Nd,x), _(Nd,x), 108 /* 0970 */ _(x,x), _(x,x), _(VI,x), _(VI,x), _(VI,x), _(VI,x), _(VI,x), _(VI,x), 113 /* 0980 */ _(x,x), _(Bi,x), _(Bi,x), _(Vs,x), _(x,x), _(VI,x), _(VI,x), _(VI,x), 114 /* 0988 */ _(VI,x), _(VI,x), _(VI,x), _(VI,x), _(VI,x), _(x,x), _(x,x), _(VI,x), 115 /* 0990 */ _(VI,x), _(x,x), _(x,x), _(VI,x), _(VI,x), _(C,x), _(C,x), _(C,x), 125 /* 09E0 */ _(VI,x), _(VI,x), _(M,B), _(M,B), _(x,x), _(x,x), _(Nd,x), _(Nd,x), 132 /* 0A00 */ _(x,x), _(Bi,x), _(Bi,x), _(Vs,x), _(x,x), _(VI,x), _(VI,x), _(VI,x), [all …]
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/external/llvm/test/CodeGen/R600/ |
D | llvm.AMDGPU.rsq.clamped.f64.ll | 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check… 9 ; VI: v_rsq_f64_e32 [[RSQ:v\[[0-9]+:[0-9]+\]]], s[2:3] 11 ; VI: s_mov_b32 s[[ALLBITS:[0-9+]]], -1 12 ; VI: s_mov_b32 s[[HIGH1:[0-9+]]], 0x7fefffff 13 ; VI: s_mov_b32 s[[LOW1:[0-9+]]], s[[ALLBITS]] 14 ; VI: v_min_f64 v[0:1], [[RSQ]], s{{\[}}[[LOW1]]:[[HIGH1]]] 15 ; VI: s_mov_b32 s[[HIGH2:[0-9+]]], 0xffefffff 16 ; VI: s_mov_b32 s[[LOW2:[0-9+]]], s[[ALLBITS]] 17 ; VI: v_max_f64 v[0:1], v[0:1], s{{\[}}[[LOW2]]:[[HIGH2]]]
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D | shl.ll | 3 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=VI %s 13 ;VI: {{^}}shl_v2i32: 14 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 15 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 38 ;VI: {{^}}shl_v4i32: 39 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 40 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 41 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 42 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 68 ;VI: {{^}}shl_i64: [all …]
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D | sra.ll | 3 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=VI %s 13 ;VI-LABEL: {{^}}ashr_v2i32: 14 ;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 15 ;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 38 ;VI-LABEL: {{^}}ashr_v4i32: 39 ;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 40 ;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 41 ;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 42 ;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 59 ;VI-LABEL: {{^}}ashr_i64: [all …]
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D | llvm.AMDGPU.rsq.clamped.ll | 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check… 11 ; VI: v_rsq_f32_e32 [[RSQ:v[0-9]+]], {{s[0-9]+}} 12 ; VI: v_min_f32_e32 [[MIN:v[0-9]+]], 0x7f7fffff, [[RSQ]] 14 ; VI: v_mov_b32_e32 [[MINFLT:v[0-9]+]], 0xff7fffff 15 ; VI: v_max_f32_e32 {{v[0-9]+}}, [[MIN]], [[MINFLT]]
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D | srl.ll | 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check… 7 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 22 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 23 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 42 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 43 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 44 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 45 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 62 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 88 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} [all …]
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D | schedule-kernel-arg-loads.ll | 2 …ga -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=VI --check-prefix=GCN %s 9 ; VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x24 10 ; VI-NEXT: s_nop 0 11 ; VI-NEXT: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c 12 ; VI-NEXT: s_nop 0 13 ; VI-NEXT: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34 14 ; VI-NEXT: s_nop 0 15 ; VI-NEXT: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x38
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D | atomic_cmp_swap_local.ll | 3 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check… 9 ; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c 10 ; VI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 28 ; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c 29 ; VI: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34 61 ; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x24 62 ; VI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x28 78 ; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x24 79 ; VI: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c
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D | 64bit-kernel-args.ll | 2 …-march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=GCN --check-prefix=VI 7 ; VI-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0x24 8 ; VI-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0x2c
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D | use-sgpr-multiple-times.ll | 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check… 32 ; VI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c 33 ; VI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 46 ; VI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c 47 ; VI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 60 ; VI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c 61 ; VI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
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D | llvm.AMDGPU.div_fixup.ll | 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check… 11 ; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c 12 ; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x34 13 ; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
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D | udivrem64.ll | 2 ;RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=VI --chec… 71 ;VI-NOT: v_lshrrev_b64 145 ;VI-NOT: v_lshrrev_b64 160 ;VI-NOT: v_lshrrev_b64 177 ;VI-NOT: v_lshrrev_b64 195 ;VI-NOT: v_lshrrev_b64 214 ;VI-NOT: v_lshrrev_b64
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D | sdivrem64.ll | 2 ;RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=VI --chec… 71 ;VI-NOT: v_lshrrev_b64 145 ;VI-NOT: v_lshrrev_b64 160 ;VI-NOT: v_lshrrev_b64 177 ;VI-NOT: v_lshrrev_b64 197 ;VI-NOT: v_lshrrev_b64 217 ;VI-NOT: v_lshrrev_b64
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D | smrd.ll | 2 …u=tonga -show-mc-encoding -verify-machineinstrs | FileCheck --check-prefix=VI --check-prefix=GCN %s 7 ; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 19 ; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc 32 ; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400 53 ; TODO: Add VI checks 66 ; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x10 80 ; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc 95 ; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400
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D | work-item-intrinsics.ll | 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check… 25 ; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4 40 ; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8 55 ; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xc 70 ; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x10 85 ; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x14 100 ; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x18 115 ; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1c 130 ; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x20 145 ; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c
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D | operand-spacing.ll | 2 …nga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=VI -check-prefix=GCN %s 9 ; VI-DAG: s_load_dword [[SREGA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c 10 ; VI-DAG: s_load_dword [[SREGB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
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D | kernel-args.ll | 2 ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=VI --… 20 ; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c 32 ; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c 55 ; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c 67 ; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c 79 ; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c 89 ; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c 122 ; VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x2c 133 ; VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x2c 164 ; VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34 [all …]
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D | rotl.i64.ll | 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check… 22 ; VI-DAG: v_lshlrev_b64 25 ; VI: v_lshrrev_b64
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D | imm.ll | 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check… 328 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 339 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 350 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 361 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 372 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 383 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 394 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 405 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 416 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c [all …]
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/external/llvm/lib/IR/ |
D | ValueSymbolTable.cpp | 27 for (iterator VI = vmap.begin(), VE = vmap.end(); VI != VE; ++VI) in ~ValueSymbolTable() local 29 << *VI->getValue()->getType() << "' Name = '" in ~ValueSymbolTable() 30 << VI->getKeyData() << "'\n"; in ~ValueSymbolTable()
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/external/clang/test/CodeGenCXX/ |
D | mangle-alias-template.cpp | 16 vector<int> VI; in z() local 17 f(VI); in z() 24 h<Vec>(VI); in z()
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/external/llvm/lib/CodeGen/ |
D | LiveVariables.cpp | 683 VarInfo &VI = getVarInfo(Reg); in replaceKillInstruction() local 684 std::replace(VI.Kills.begin(), VI.Kills.end(), OldMI, NewMI); in replaceKillInstruction() 739 LiveVariables::VarInfo &VI = getVarInfo(Reg); in isLiveOut() local 750 if (VI.AliveBlocks.test(SuccIdx)) in isLiveOut() 760 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i) in isLiveOut() 761 if (VI.Kills[i]->getParent() == SuccMBB) in isLiveOut() 767 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i) in isLiveOut() 768 if (VI.Kills[i]->getParent() == SuccMBB1 || in isLiveOut() 769 VI.Kills[i]->getParent() == SuccMBB2) in isLiveOut() 775 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i) in isLiveOut() [all …]
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D | DFAPacketizer.cpp | 196 for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(), in PacketizeMIs() local 197 VE = CurrentPacketMIs.end(); VI != VE; ++VI) { in PacketizeMIs() 198 MachineInstr *MJ = *VI; in PacketizeMIs()
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/external/llvm/lib/Target/R600/ |
D | VIInstructions.td | 1 //===-- VIInstructions.td - VI Instruction Defintions ---------------------===// 9 // Instruction definitions for VI and newer.
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/external/clang/test/CXX/drs/ |
D | dr4xx.cpp | 719 typedef volatile int VI; typedef 720 void f(int *a, CI *b, VI *c) { in f() 723 a->~VI(); in f() 726 a->VI::~VI(); in f() 728 a->CI::~VI(); // FIXME: This is invalid; CI and VI are not the same scalar type. in f() 732 b->~VI(); in f() 735 b->VI::~VI(); in f() 739 c->~VI(); in f() 742 c->VI::~VI(); in f()
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