Searched refs:VLIW (Results 1 – 12 of 12) sorted by relevance
10 // R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction
50 setSchedulingPreference(Sched::VLIW); in R600TargetLowering()
102 Generate DFA Packetizer for VLIW targets.
100 D: Deterministic finite automaton based infrastructure for VLIW packetization238 D: Implemented DFA-based target independent VLIW packetizer284 D: Backend for Qualcomm's Hexagon VLIW processor.
106 D: VLIW Instruction Scheduling, Packetization
180 on a VLIW architecture. The class internally generates a deterministic finite
527 bundles. A MI bundle can model a VLIW group / pack which contains an arbitrary1586 VLIW Packetizer1589 In a Very Long Instruction Word (VLIW) architecture, the compiler is responsible1592 *bundles*. The VLIW packetizer in LLVM is a target-independent mechanism to1598 Instructions in a VLIW target can typically be mapped to multiple functional1603 VLIW packetizer parses the instruction classes of a target and generates tables1622 To generate tables for a VLIW target, add *Target*\ GenDFAPacketizer.inc as a
73 VLIW // Scheduling for VLIW targets. enumerator
304 if (TLI->getSchedulingPreference() == Sched::VLIW) in createDefaultScheduler()
1788 setSchedulingPreference(Sched::VLIW); in HexagonTargetLowering()
700 - Ignored on older VLIW subtargets which did not have separate scalar