Searched refs:VTRN (Results 1 – 13 of 13) sorted by relevance
| /external/llvm/test/MC/ARM/ |
| D | neon-shuffle-encoding.s | 79 @ VTRN alternate size suffices
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| /external/llvm/test/CodeGen/ARM/ |
| D | vzip.ll | 27 ; VZIP.32 is equivalent to VTRN.32 for 64-bit vectors.
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| D | vuzp.ll | 27 ; VUZP.32 is equivalent to VTRN.32 for 64-bit vectors.
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| D | vtrn.ll | 99 ; Undef shuffle indices should not prevent matching to VTRN:
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-trn.ll | 108 ; Undef shuffle indices should not prevent matching to VTRN:
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 157 VTRN, // transpose enumerator
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| D | ARMScheduleSwift.td | 1614 (instregex "VSWP", "VTRN", "VUZP", "VZIP")>;
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| D | ARMISelLowering.cpp | 1102 case ARMISD::VTRN: return "ARMISD::VTRN"; in getTargetNodeName()
5441 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), in GeneratePerfectShuffle()
5557 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), in LowerVECTOR_SHUFFLE()
5567 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), in LowerVECTOR_SHUFFLE()
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| D | ARMISelDAGToDAG.cpp | 2779 case ARMISD::VTRN: { in Select()
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| D | ARMInstrNEON.td | 583 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
2532 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
6080 // VTRN : Vector Transpose
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| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 786 def VTRN : WInst<"vtrn", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
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| /external/valgrind/none/tests/arm/ |
| D | neon128.stdout.exp | 2131 ---- VTRN ----
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| D | neon64.stdout.exp | 3380 ---- VTRN ----
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