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/external/llvm/test/MC/Mips/
Dmips-register-names-o32.s4 # Second byte of addiu with $zero at rt contains the number of the source
8 addiu $zero, $zero, 0 # CHECK: encoding: [0x24,0x00,0x00,0x00] label
9 addiu $at, $zero, 0 # CHECK: encoding: [0x24,0x01,0x00,0x00] label
10 addiu $v0, $zero, 0 # CHECK: encoding: [0x24,0x02,0x00,0x00] label
11 addiu $v1, $zero, 0 # CHECK: encoding: [0x24,0x03,0x00,0x00] label
12 addiu $a0, $zero, 0 # CHECK: encoding: [0x24,0x04,0x00,0x00] label
13 addiu $a1, $zero, 0 # CHECK: encoding: [0x24,0x05,0x00,0x00] label
14 addiu $a2, $zero, 0 # CHECK: encoding: [0x24,0x06,0x00,0x00] label
15 addiu $a3, $zero, 0 # CHECK: encoding: [0x24,0x07,0x00,0x00] label
16 addiu $t0, $zero, 0 # CHECK: encoding: [0x24,0x08,0x00,0x00] label
[all …]
Ddo_switch2.s26 addiu $2, $2, %lo(_gp_disp)
27 addiu $sp, $sp, -8
28 addiu $1, $zero, 2
35 addiu $2, $zero, 4
37 addiu $sp, $sp, 8
47 addiu $2, $zero, 1
49 addiu $sp, $sp, 8
51 addiu $2, $zero, 2
53 addiu $sp, $sp, 8
55 addiu $2, $zero, 0
[all …]
Ddo_switch1.s26 addiu $sp, $sp, -8
27 addiu $1, $zero, 2
34 addiu $2, $zero, 4
36 addiu $sp, $sp, 8
45 addiu $2, $zero, 1
47 addiu $sp, $sp, 8
49 addiu $2, $zero, 2
51 addiu $sp, $sp, 8
53 addiu $2, $zero, 0
55 addiu $sp, $sp, 8
[all …]
Delf-tls.s32 addiu $2, $2, %lo(_gp_disp)
33 addiu $sp, $sp, -24
38 addiu $4, $gp, %tlsgd(t1)
42 addiu $sp, $sp, 24
64 addiu $2, $2, %lo(_gp_disp)
65 addiu $sp, $sp, -24
70 addiu $4, $gp, %tlsgd(t2)
74 addiu $sp, $sp, 24
96 addiu $2, $2, %lo(_gp_disp)
97 addiu $sp, $sp, -24
[all …]
Dsort-relocation-table.s48 addiu $2,$2,%lo(sym4) label
49 addiu $2,$2,%lo(sym4) label
89 addiu $2,$2,%lo(sym8) label
97 addiu $2,$2,%lo(symc1) label
98 addiu $2,$2,%lo(symc1) label
99 addiu $2,$2,%lo(symc1) label
102 addiu $2,$2,%lo(symc2) label
107 addiu $2,$2,%lo(symc1) label
108 addiu $2,$2,%lo(symc2) label
Ddo_switch3.s28 addiu $1, $zero, 2
36 addiu $2, $zero, 4
52 addiu $2, $zero, 1
56 addiu $2, $zero, 2
60 addiu $2, $zero, 0
64 addiu $2, $zero, 3
Dmips-alu-instructions.s76 # CHECK: addiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x24]
79 # CHECK: addiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x24]
80 # CHECK: addiu $11, $11, 40 # encoding: [0x28,0x00,0x6b,0x25]
91 # CHECK: addiu $sp, $sp, -40 # encoding: [0xd8,0xff,0xbd,0x27]
104 addiu $9,$6,-15001
105 addiu $11,40
129 # CHECK: addiu $9, $9, 10 # encoding: [0x0a,0x00,0x29,0x25]
136 # CHECK: addiu $9, $9, -10 # encoding: [0xf6,0xff,0x29,0x25]
Dmicromips-relocations.s15 # CHECK-FIXUP: addiu $2, $2, %lo(_gp_disp)
35 # CHECK-FIXUP: addiu $2, $2, %dtprel_lo(_gp_disp)
65 # CHECK-FIXUP: addiu $2, $2, %tprel_lo(_gp_disp)
70 # CHECK-FIXUP: addiu $4, $gp, %tlsgd(a)
74 # CHECK-FIXUP: addiu $4, $gp, %tlsldm(f.i)
99 addiu $2, $2, %lo(_gp_disp)
103 addiu $2, $2, %dtprel_lo(_gp_disp)
109 addiu $2, $2, %tprel_lo(_gp_disp)
110 addiu $4, $gp, %tlsgd(a)
111 addiu $4, $gp, %tlsldm(f.i)
Delf-gprel-32-64.s46 addiu $2, $zero, -1
58 addiu $2, $zero, 1
64 addiu $2, $zero, 3
67 addiu $2, $zero, 2
70 addiu $2, $zero, 7
/external/llvm/test/CodeGen/Mips/
Dcmov.ll15 ; 32-CMOV-DAG: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1)
20 ; 32-CMP-DAG: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1)
54 ; 32-CMOV-DAG: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(d)
55 ; 32-CMOV-DAG: addiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got(c)
59 ; 32-CMP-DAG: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(d)
60 ; 32-CMP-DAG: addiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got(c)
125 ; FIXME: Use xori instead of addiu+xor.
126 ; 32-CMOV: addiu $[[R0:[0-9]+]], $zero, 234
135 ; FIXME: Use xori instead of addiu+xor.
136 ; 64-CMOV: addiu $[[R0:[0-9]+]], $zero, 234
[all …]
Dinlineasm_constraint.ll8 ; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},4096
10 tail call i16 asm sideeffect "addiu $0,$1,$2", "=r,r,I"(i16 7, i16 4096) nounwind
14 ; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3
16 tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,I"(i32 7, i32 -3) nounwind
20 ; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},0
22 tail call i32 asm sideeffect "addiu $0,$1,$2\0A\09 ", "=r,r,J"(i32 7, i16 0) nounwind
38 ; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3
40 tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,N"(i32 7, i32 -3) nounwind
44 ; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3
46 tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,O"(i32 7, i16 -3) nounwind
[all …]
Do32_cc.ll57 ; ALL-DAG: addiu $4, $zero, 12
58 ; ALL-DAG: addiu $5, $zero, 13
59 ; ALL-DAG: addiu $6, $zero, 14
60 ; ALL-DAG: addiu $7, $zero, 15
72 ; ALL-DAG: addiu $6, $zero, 23
86 ; ALL-DAG: addiu $6, $zero, 33
87 ; ALL-DAG: addiu $7, $zero, 24
99 ; ALL-DAG: addiu $5, $zero, 43
100 ; ALL-DAG: addiu $6, $zero, 34
111 ; ALL-DAG: addiu $4, $zero, 22
[all …]
Dinlineasm-cnstrnt-reg.ll11 ;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},23
13 tail call i8 asm sideeffect "addiu $0,$1,$2", "=r,r,n"(i8 27, i8 23) nounwind
17 ;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},13
19 tail call i16 asm sideeffect "addiu $0,$1,$2", "=r,r,n"(i16 17, i16 13) nounwind
23 ;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},3
25 tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,n"(i32 7, i32 3) nounwind
29 ; CHECK: addiu $25,${{[0-9]+}},1024
31 tail call i32 asm sideeffect "addiu $0,$1,$2", "=c,c,I"(i32 4194304, i32 1024) nounwind
Dlongbranch.ll33 ; CHECK: addiu $[[R0]], $[[R0]], %lo(_gp_disp)
37 ; CHECK: addiu $[[R2:[0-9]+]], $zero, 1
51 ; O32: addiu $[[R0]], $[[R0]], %lo(_gp_disp)
56 ; O32: addiu $sp, $sp, -8
60 ; O32-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]]))
65 ; O32-NEXT: addiu $sp, $sp, 8
69 ; O32: addiu $[[R2:[0-9]+]], $zero, 1
98 ; N64: addiu $[[R3:[0-9]+]], $zero, 1
108 ; MICROMIPS: addiu $[[R0]], $[[R0]], %lo(_gp_disp)
113 ; MICROMIPS: addiu $sp, $sp, -8
[all …]
Dfcmp.ll18 ; ALL: addiu $2, $zero, 0
28 ; 32-C-DAG: addiu $2, $zero, 1
32 ; 64-C-DAG: addiu $2, $zero, 1
52 ; 32-C-DAG: addiu $2, $zero, 1
56 ; 64-C-DAG: addiu $2, $zero, 1
76 ; 32-C-DAG: addiu $2, $zero, 1
80 ; 64-C-DAG: addiu $2, $zero, 1
100 ; 32-C-DAG: addiu $2, $zero, 1
104 ; 64-C-DAG: addiu $2, $zero, 1
124 ; 32-C-DAG: addiu $2, $zero, 1
[all …]
Do32_cc_vararg.ll31 ; CHECK: addiu $sp, $sp, -16
57 ; CHECK: addiu $sp, $sp, -16
61 ; CHECK: addiu $[[R0:[0-9]+]], $sp, 20
62 ; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
63 ; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
85 ; CHECK: addiu $sp, $sp, -16
108 ; CHECK: addiu $sp, $sp, -24
111 ; CHECK: addiu ${{[0-9]+}}, $sp, 32
136 ; CHECK: addiu $sp, $sp, -24
162 ; CHECK: addiu $sp, $sp, -24
[all …]
Dcttz-v.ll8 ; MIPS32-DAG: addiu $[[R0:[0-9]+]], $4, -1
12 ; MIPS32-DAG: addiu $[[R4:[0-9]+]], $zero, 32
14 ; MIPS32-DAG: addiu $[[R5:[0-9]+]], $5, -1
22 ; MIPS64-DAG: addiu $[[R0:[0-9]+]], $[[A0]], -1
26 ; MIPS64-DAG: addiu $[[R4:[0-9]+]], $zero, 32
29 ; MIPS64-DAG: addiu $[[R5:[0-9]+]], $[[A1]], -1
Dinlineasm-operand-code.ll15 ;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},0xfffffffffffffffd
17 tail call i32 asm sideeffect "addiu $0,$1,${2:X}", "=r,r,I"(i32 7, i32 -3) ;
26 ;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},0xfffd
28 tail call i32 asm sideeffect "addiu $0,$1,${2:x}", "=r,r,I"(i32 7, i32 -3) ;
37 ;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},-3
39 tail call i32 asm sideeffect "addiu $0,$1,${2:d}", "=r,r,I"(i32 7, i32 -3) ;
48 ;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},-4
50 tail call i32 asm sideeffect "addiu $0,$1,${2:m}", "=r,r,I"(i32 7, i32 -3) ;
59 ;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},-3
61 tail call i32 asm sideeffect "addiu $0,$1,${2:z}", "=r,r,I"(i32 7, i32 -3) ;
[all …]
Deh-dwarf-cfa.ll16 ; CHECK: addiu $sp, $sp, -32
17 ; CHECK: addiu $2, $sp, 32
29 ; CHECK: addiu $[[R0]], $[[R0]], -8
35 ; CHECK: addiu $2, $[[R1]], 8
49 ; CHECK: addiu $sp, $sp, -40
52 ; CHECK: addiu $[[R0:[a-z0-9]+]], $fp, 40
/external/llvm/test/CodeGen/Mips/cconv/
Darguments-varargs.ll23 ; O32: addiu [[SP:\$sp]], $sp, -8
24 ; N32: addiu [[SP:\$sp]], $sp, -64
46 ; O32-DAG: addiu [[VA:\$[0-9]+]], [[SP]], 12
49 ; N32-DAG: addiu [[VA:\$[0-9]+]], [[SP]], 8
62 ; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4
66 ; N32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 8
70 ; N64-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 8
84 ; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords)
86 ; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords)
96 ; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4
[all …]
Dstack-alignment.ll23 ; O32: addiu $sp, $sp, -8
24 ; O32: addiu $sp, $sp, 8
25 ; N32: addiu $sp, $sp, -16
26 ; N32: addiu $sp, $sp, 16
27 ; N64: addiu $sp, $sp, -16
28 ; N64: addiu $sp, $sp, 16
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dfpcmpa.ll23 ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
24 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
44 ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
45 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
64 ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
65 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
85 ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
86 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
105 ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
106 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
[all …]
Dlogopm.ll34 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
57 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
80 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
83 ; CHECK-DAG: addiu $[[CONST:[0-9]+]], $zero, 1
105 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
128 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
149 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
152 ; CHECK-DAG: addiu $[[CONST:[0-9]+]], $zero, 1
174 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
197 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
[all …]
Dcallabi.ll25 ; CHECK-DAG: addiu $4, $zero, 10
39 ; CHECK-DAG: addiu $4, $zero, 746
40 ; CHECK-DAG: addiu $5, $zero, 892
54 ; CHECK-DAG: addiu $4, $zero, 88
55 ; CHECK-DAG: addiu $5, $zero, 44
56 ; CHECK-DAG: addiu $6, $zero, 11
69 ; CHECK-DAG: addiu $4, $zero, 167
70 ; CHECK-DAG: addiu $5, $zero, 320
71 ; CHECK-DAG: addiu $6, $zero, 97
72 ; CHECK-DAG: addiu $7, $zero, 14
[all …]
/external/valgrind/coregrind/m_dispatch/
Ddispatch-mips32-linux.S67 addiu $29, -64
136 addiu $29, 64 /* stack_size */
156 addiu $3, $3, -16
171 addiu $3, $3, -16
181 addiu $13, $13, 0x1
214 addiu $13, $13, 0x1

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