| /external/libhevc/common/arm64/ |
| D | ihevc_deblk_luma_horz.s | 137 csneg x9,x9,x9,pl
142 csneg x8,x8,x8,pl // dp0 value is stored in x8
166 csneg x12,x12,x12,pl
172 csneg x11,x11,x11,pl // dp3 value is stored in x8
228 csneg x2,x2,x2,pl
231 csneg x8,x8,x8,pl
240 csneg x7,x7,x7,pl
284 csneg x8,x8,x8,pl
288 csneg x2,x2,x2,pl
298 csneg x7,x7,x7,pl
|
| D | ihevc_deblk_luma_vert.s | 130 csneg x9,x9,x9,pl
140 csneg x8,x8,x8,pl
165 csneg x12,x12,x12,pl
171 csneg x11,x11,x11,pl // dp3 value is stored in x8
226 csneg x8,x8,x8,pl
229 csneg x2,x2,x2,pl
239 csneg x7,x7,x7,pl
279 csneg x8,x8,x8,pl
283 csneg x2,x2,x2,pl
292 csneg x7,x7,x7,pl
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | cond-sel.ll | 147 ; CHECK: csneg {{w[0-9]+}}, [[LHS]], [[RHS]], ls
155 ; CHECK: csneg {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le
164 ; CHECK: csneg {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls
172 ; CHECK: csneg {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le
|
| D | arm64-csel.ll | 83 ; CHECK-next: csneg
159 ; CHECK: csneg w0, w1, w2, ne
170 ; CHECK: csneg x0, x1, x2, ne
|
| D | arm64-early-ifcvt.ll | 186 ; CHECK-NEXT: csneg w0, w1, w0, eq
204 ; CHECK-NEXT: csneg x0, x1, x0, eq
222 ; CHECK-NEXT: csneg w0, w1, w0, ne
240 ; CHECK-NEXT: csneg x0, x1, x0, ne
|
| /external/valgrind/none/tests/arm64/ |
| D | integer.stdout.exp | 875 cmp x17,x18 ; csneg x16,x17,x18,eq :: rd 8593c2e5aedb9b6b rm afa6ef803bc9291c, rn 7a6c3d1a51246495,…
876 cmp x17,x18 ; csneg x16,x17,x18,ne :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495,…
877 cmp x17,x18 ; csneg x16,x17,x18,cc :: rd 8593c2e5aedb9b6b rm afa6ef803bc9291c, rn 7a6c3d1a51246495,…
878 cmp x17,x18 ; csneg x16,x17,x18,cs :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495,…
879 cmp x17,x18 ; csneg x16,x17,x18,mi :: rd 8593c2e5aedb9b6b rm afa6ef803bc9291c, rn 7a6c3d1a51246495,…
880 cmp x17,x18 ; csneg x16,x17,x18,pl :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495,…
881 cmp x17,x18 ; csneg x16,x17,x18,vc :: rd 8593c2e5aedb9b6b rm afa6ef803bc9291c, rn 7a6c3d1a51246495,…
882 cmp x17,x18 ; csneg x16,x17,x18,vs :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495,…
908 cmp w17,w18 ; csneg w16,w17,w18,eq :: rd 00000000aedb9b6b rm afa6ef803bc9291c, rn 7a6c3d1a51246495,…
909 cmp w17,w18 ; csneg w16,w17,w18,ne :: rd 000000003bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495,…
[all …]
|
| /external/llvm/test/MC/AArch64/ |
| D | basic-a64-instructions.s | 1373 csneg w1, w0, w19, ne
1374 csneg wzr, w5, w9, eq
1375 csneg w9, wzr, w30, gt
1376 csneg w1, w28, wzr, mi
1382 csneg x19, x23, x29, lt
1383 csneg xzr, x3, x4, ge
1384 csneg x5, xzr, x6, cs
1385 csneg x7, x8, xzr, cc
|
| D | arm64-arithmetic-encoding.s | 556 csneg w1, w2, w3, eq
557 csneg x1, x2, x3, eq
|
| D | basic-a64-diagnostics.s | 1358 csneg w20, w21, wsp, mi
1359 csneg x0, sp, x29, le
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-arithmetic.txt | 524 # CHECK: csneg w1, w2, w3, eq
526 # CHECK: csneg x1, x2, x3, eq
|
| D | basic-a64-instructions.txt | 927 # CHECK: csneg w1, w0, w19, ne
928 # CHECK: csneg wzr, w5, w9, eq
929 # CHECK: csneg w9, wzr, w30, gt
930 # CHECK: csneg w1, w28, wzr, mi
931 # CHECK: csneg x19, x23, x29, lt
932 # CHECK: csneg xzr, x3, x4, ge
933 # CHECK: csneg x5, xzr, x6, hs
934 # CHECK: csneg x7, x8, xzr, lo
1001 # CHECK: csneg x4, x8, x8, al
|
| /external/v8/test/cctest/ |
| D | test-disasm-arm64.cc | 1292 COMPARE(csneg(w18, w19, w20, vs), "csneg w18, w19, w20, vs"); in TEST_()
1293 COMPARE(csneg(x21, x22, x23, vc), "csneg x21, x22, x23, vc"); in TEST_()
1311 COMPARE(csneg(x6, x7, x8, al), "csneg x6, x7, x8, al"); in TEST_()
1312 COMPARE(csneg(x7, x8, x9, nv), "csneg x7, x8, x9, nv"); in TEST_()
|
| /external/v8/src/arm64/ |
| D | assembler-arm64.cc | 1352 void Assembler::csneg(const Register& rd, in csneg() function in v8::internal::Assembler
1388 csneg(rd, rn, rn, NegateCondition(cond)); in cneg()
|
| D | macro-assembler-arm64-inl.h | 510 csneg(rd, rn, rm, cond); in Csneg()
|
| D | assembler-arm64.h | 1351 void csneg(const Register& rd,
|
| /external/vixl/test/ |
| D | test-disasm-a64.cc | 2163 COMPARE(csneg(w18, w19, w20, vs), "csneg w18, w19, w20, vs"); in TEST()
2164 COMPARE(csneg(x21, x22, x23, vc), "csneg x21, x22, x23, vc"); in TEST()
2182 COMPARE(csneg(x6, x7, x8, al), "csneg x6, x7, x8, al"); in TEST()
2183 COMPARE(csneg(x7, x8, x9, nv), "csneg x7, x8, x9, nv"); in TEST()
|
| /external/vixl/src/vixl/a64/ |
| D | assembler-a64.cc | 1123 void Assembler::csneg(const Register& rd, in csneg() function in vixl::Assembler
1159 csneg(rd, rn, rn, InvertCondition(cond)); in cneg()
|
| D | macro-assembler-a64.h | 1118 csneg(rd, rn, rm, cond); in Csneg()
|
| D | assembler-a64.h | 1495 void csneg(const Register& rd,
|
| /external/vixl/doc/ |
| D | supported-instructions.md | 443 void csneg(const Register& rd,
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 969 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
|