Searched refs:dmb (Results 1 – 25 of 56) sorted by relevance
123
| /external/llvm/test/CodeGen/ARM/ |
| D | optimize-dmbs-v7.ll | 23 ; Hence it should have 3 dmb;str;dmb sequences with the middle dmbs collapsed
26 ; CHECK: dmb
27 ; CHECK-NOT: dmb
31 ; CHECK: dmb
32 ; CHECK-NOT: dmb
36 ; CHECK: dmb
37 ; CHECK-NOT: dmb
41 ; CHECK: dmb
42 ; CHECK-NOT: dmb
48 call void @llvm.arm.dmb(i32 11)
[all …]
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| D | atomic-load-store.ll | 11 ; ARM: dmb {{ish$}}
13 ; ARM-NEXT: dmb {{ish$}}
17 ; THUMBTWO: dmb {{ish$}}
19 ; THUMBTWO-NEXT: dmb {{ish$}}
25 ; THUMBM: dmb sy
27 ; THUMBM: dmb sy
35 ; ARM-NEXT: dmb {{ish$}}
40 ; THUMBTWO-NEXT: dmb {{ish$}}
46 ; THUMBM: dmb sy
53 ; ARM-NOT: dmb
[all …]
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| D | swift-atomics.ll | 4 ; Release operations only need the store barrier provided by a "dmb ishst",
8 ; CHECK: dmb ishst
12 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
18 ; followed by an acquire does not get reordered. In that case a "dmb ishst" is
22 ; CHECK: dmb ishst
24 ; CHECK: dmb {{ish$}}
26 ; CHECK: dmb {{ish$}}
29 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
31 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
33 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
[all …]
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| D | atomic-64bit.ll | 8 ; CHECK: dmb {{ish$}}
17 ; CHECK: dmb {{ish$}}
20 ; CHECK-THUMB: dmb {{ish$}}
29 ; CHECK-THUMB: dmb {{ish$}}
37 ; CHECK: dmb {{ish$}}
46 ; CHECK: dmb {{ish$}}
49 ; CHECK-THUMB: dmb {{ish$}}
58 ; CHECK-THUMB: dmb {{ish$}}
66 ; CHECK: dmb {{ish$}}
75 ; CHECK: dmb {{ish$}}
[all …]
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| D | atomic-ops-v8.ll | 14 ; CHECK-NOT: dmb
27 ; CHECK-NOT: dmb
37 ; CHECK-NOT: dmb
50 ; CHECK-NOT: dmb
60 ; CHECK-NOT: dmb
73 ; CHECK-NOT: dmb
83 ; CHECK-NOT: dmb
99 ; CHECK-NOT: dmb
110 ; CHECK-NOT: dmb
123 ; CHECK-NOT: dmb
[all …]
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| D | intrinsics-v8.ll | 4 ; CHECK: dmb sy
5 call void @llvm.arm.dmb(i32 15)
6 ; CHECK: dmb osh
7 call void @llvm.arm.dmb(i32 3)
17 declare void @llvm.arm.dmb(i32)
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| D | cmpxchg-idioms.ll | 6 ; CHECK: dmb ishst
19 ; CHECK: dmb ish
25 ; CHECK: dmb ish
38 ; CHECK: dmb ishst
70 ; CHECK: dmb ishst
82 ; CHECK: dmb ish
87 ; CHECK: dmb ish
|
| D | print-memb-operand.ll | 3 ; CHECK: dmb ld
6 call void @llvm.arm.dmb(i32 13)
10 declare void @llvm.arm.dmb(i32)
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| D | intrinsics-memory-barrier.ll | 6 call void @llvm.arm.dmb(i32 3) ; CHECK: dmb osh
19 call void @llvm.arm.dmb(i32 15) ; CHECK: dmb sy
53 declare void @llvm.arm.dmb(i32)
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| D | cmpxchg-weak.ll | 8 ; CHECK: dmb ish
14 ; CHECK: dmb ish
30 ; CHECK: dmb ish
37 ; CHECK: dmb ish
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| D | atomic-op.ll | 275 ; CHECK: dmb ish
283 ; CHECK: dmb ish
294 ; CHECK-NOT: dmb ish
303 ; CHECK: dmb ish
316 ; CHECK: dmb
318 ; CHECK: dmb
325 ; CHECK-BAREMETAL-NOT: dmb
327 ; CHECK-BAREMETAL-NOT: dmb
338 ; CHECK: dmb
340 ; CHECK: dmb
[all …]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | atomic-ops.ll | 18 ; CHECK-NOT: dmb
29 ; CHECK-NOT: dmb
38 ; CHECK-NOT: dmb
49 ; CHECK-NOT: dmb
58 ; CHECK-NOT: dmb
69 ; CHECK-NOT: dmb
78 ; CHECK-NOT: dmb
89 ; CHECK-NOT: dmb
98 ; CHECK-NOT: dmb
109 ; CHECK-NOT: dmb
[all …]
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| D | intrinsics-memory-barrier.ll | 4 ; CHECK: dmb sy
5 call void @llvm.aarch64.dmb(i32 15)
6 ; CHECK: dmb osh
7 call void @llvm.aarch64.dmb(i32 3)
23 call void @llvm.aarch64.dmb(i32 15); CHECK: dmb sy
55 declare void @llvm.aarch64.dmb(i32)
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| D | arm64-atomic-128.ll | 169 ; CHECK-NOT: dmb
171 ; CHECK-NOT: dmb
178 ; CHECK-NOT: dmb
180 ; CHECK-NOT: dmb
188 ; CHECK-NOT: dmb
193 ; CHECK-NOT: dmb
200 ; CHECK-NOT: dmb
205 ; CHECK-NOT: dmb
212 ; CHECK-NOT: dmb
217 ; CHECK-NOT: dmb
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| D | atomic-ops-not-barriers.ll | 16 ; CHECK: dmb
18 ; CHECK: dmb
19 ; The key point here is that the second dmb isn't immediately followed by the
|
| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions-v8.s | 22 dmb ishld
23 dmb oshld
24 dmb nshld
25 dmb ld
27 @ CHECK-V8: dmb ishld @ encoding: [0x59,0xf0,0x7f,0xf5]
28 @ CHECK-V8: dmb oshld @ encoding: [0x51,0xf0,0x7f,0xf5]
29 @ CHECK-V8: dmb nshld @ encoding: [0x55,0xf0,0x7f,0xf5]
30 @ CHECK-V8: dmb ld @ encoding: [0x5d,0xf0,0x7f,0xf5]
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| D | basic-thumb2-instructions-v8.s | 41 dmb ishld
42 dmb oshld
43 dmb nshld
44 dmb ld
46 @ CHECK-V8: dmb ishld @ encoding: [0xbf,0xf3,0x59,0x8f]
47 @ CHECK-V8: dmb oshld @ encoding: [0xbf,0xf3,0x51,0x8f]
48 @ CHECK-V8: dmb nshld @ encoding: [0xbf,0xf3,0x55,0x8f]
49 @ CHECK-V8: dmb ld @ encoding: [0xbf,0xf3,0x5d,0x8f]
|
| D | thumb-hints.s | 22 dmb sy
23 dmb
28 @ CHECK: dmb sy @ encoding: [0xbf,0xf3,0x5f,0x8f]
29 @ CHECK: dmb sy @ encoding: [0xbf,0xf3,0x5f,0x8f]
49 @ CHECK-ERROR-NEXT: dmb sy
52 @ CHECK-ERROR-NEXT: dmb
|
| D | invalid-barrier.s | 7 dmb #0x10
8 dmb imaginary_scope
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| /external/llvm/test/Transforms/AtomicExpand/ARM/ |
| D | atomic-expansion-v7.ll | 5 ; CHECK-NOT: dmb
15 ; CHECK-NOT: dmb
23 ; CHECK: call void @llvm.arm.dmb(i32 11)
34 ; CHECK: call void @llvm.arm.dmb(i32 11)
42 ; CHECK-NOT: dmb
51 ; CHECK: call void @llvm.arm.dmb(i32 11)
59 ; CHECK: call void @llvm.arm.dmb(i32 11)
70 ; CHECK-NOT: dmb
78 ; CHECK: call void @llvm.arm.dmb(i32 11)
90 ; CHECK: call void @llvm.arm.dmb(i32 11)
[all …]
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| D | cmpxchg-weak.ll | 5 ; Intrinsic for "dmb ishst" is then expected
6 ; CHECK: call void @llvm.arm.dmb(i32 10)
20 ; CHECK: call void @llvm.arm.dmb(i32 11)
24 ; CHECK: call void @llvm.arm.dmb(i32 11)
38 ; CHECK: call void @llvm.arm.dmb(i32 10)
52 ; CHECK: call void @llvm.arm.dmb(i32 11)
56 ; CHECK-NOT: dmb
70 ; CHECK-NOT: dmb
84 ; CHECK-NOT: dmb
88 ; CHECK-NOT: dmb
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb-v8.txt | 25 # CHECK: dmb ishld
26 # CHECK: dmb oshld
27 # CHECK: dmb nshld
28 # CHECK: dmb ld
|
| D | basic-arm-instructions-v8.txt | 17 # CHECK: dmb ishld
18 # CHECK: dmb oshld
19 # CHECK: dmb nshld
20 # CHECK: dmb ld
|
| /external/compiler-rt/lib/builtins/arm/ |
| D | sync-ops.h | 23 dmb ; \
31 dmb ; \
40 dmb ; \
48 dmb ; \
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-optional-hash.s | 20 ; CHECK: dmb osh ; encoding: [0xbf,0x33,0x03,0xd5]
21 dmb 3 label
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