| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-cvt.ll | 88 ;CHECK: fcvtms w0, s0
90 %tmp3 = call i32 @llvm.aarch64.neon.fcvtms.i32.f32(float %A)
96 ;CHECK: fcvtms x0, s0
98 %tmp3 = call i64 @llvm.aarch64.neon.fcvtms.i64.f32(float %A)
104 ;CHECK: fcvtms w0, d0
106 %tmp3 = call i32 @llvm.aarch64.neon.fcvtms.i32.f64(double %A)
112 ;CHECK: fcvtms x0, d0
114 %tmp3 = call i64 @llvm.aarch64.neon.fcvtms.i64.f64(double %A)
118 declare i32 @llvm.aarch64.neon.fcvtms.i32.f32(float) nounwind readnone
119 declare i64 @llvm.aarch64.neon.fcvtms.i64.f32(float) nounwind readnone
[all …]
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| D | arm64-vcvt.ll | 68 ;CHECK: fcvtms.2s v0, v0
70 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtms.v2i32.v2f32(<2 x float> %A)
77 ;CHECK: fcvtms.4s v0, v0
79 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtms.v4i32.v4f32(<4 x float> %A)
86 ;CHECK: fcvtms.2d v0, v0
88 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtms.v2i64.v2f64(<2 x double> %A)
92 declare <2 x i32> @llvm.aarch64.neon.fcvtms.v2i32.v2f32(<2 x float>) nounwind readnone
93 declare <4 x i32> @llvm.aarch64.neon.fcvtms.v4i32.v4f32(<4 x float>) nounwind readnone
94 declare <2 x i64> @llvm.aarch64.neon.fcvtms.v2i64.v2f64(<2 x double>) nounwind readnone
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| /external/llvm/test/MC/AArch64/ |
| D | neon-scalar-cvt.s | 101 fcvtms s22, s13
102 fcvtms d21, d14
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| D | arm64-fp-encoding.s | 180 fcvtms w1, s2
181 fcvtms w1, d2
182 fcvtms x1, s2
183 fcvtms x1, d2
185 ; CHECK: fcvtms w1, s2 ; encoding: [0x41,0x00,0x30,0x1e]
186 ; CHECK: fcvtms w1, d2 ; encoding: [0x41,0x00,0x70,0x1e]
187 ; CHECK: fcvtms x1, s2 ; encoding: [0x41,0x00,0x30,0x9e]
188 ; CHECK: fcvtms x1, d2 ; encoding: [0x41,0x00,0x70,0x9e]
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| D | neon-simd-misc.s | 545 fcvtms v6.4s, v8.4s
546 fcvtms v6.2d, v8.2d
547 fcvtms v4.2s, v0.2s
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| D | arm64-advsimd.s | 663 fcvtms.2s v0, v0
664 fcvtms.4s v0, v0
665 fcvtms.2d v0, v0
666 fcvtms s0, s0
667 fcvtms d0, d0 define
669 ; CHECK: fcvtms.2s v0, v0 ; encoding: [0x00,0xb8,0x21,0x0e]
670 ; CHECK: fcvtms.4s v0, v0 ; encoding: [0x00,0xb8,0x21,0x4e]
671 ; CHECK: fcvtms.2d v0, v0 ; encoding: [0x00,0xb8,0x61,0x4e]
672 ; CHECK: fcvtms s0, s0 ; encoding: [0x00,0xb8,0x21,0x5e]
673 ; CHECK: fcvtms d0, d0 ; encoding: [0x00,0xb8,0x61,0x5e]
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| D | neon-diagnostics.s | 5911 fcvtms v0.16b, v31.16b
5912 fcvtms v2.8h, v4.8h
5913 fcvtms v1.8b, v9.8b
5914 fcvtms v13.4h, v21.4h
7207 fcvtms s0, d0
7208 fcvtms d0, s0 define
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| D | basic-a64-instructions.s | 2073 fcvtms w2, s3
2074 fcvtms x4, s5
2127 fcvtms w2, d3
2128 fcvtms x4, d5
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| /external/v8/test/cctest/ |
| D | test-disasm-arm64.cc | 1558 COMPARE(fcvtms(w0, s1), "fcvtms w0, s1"); in TEST_()
1559 COMPARE(fcvtms(x2, s3), "fcvtms x2, s3"); in TEST_()
1560 COMPARE(fcvtms(w4, d5), "fcvtms w4, d5"); in TEST_()
1561 COMPARE(fcvtms(x6, d7), "fcvtms x6, d7"); in TEST_()
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| D | test-assembler-arm64.cc | 7027 TEST(fcvtms) { in TEST() argument
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| /external/vixl/test/ |
| D | test-simulator-a64.cc | 2543 DEFINE_TEST_FP_TO_INT(fcvtms, FPToS, Conversions) in DEFINE_TEST_FP_TO_INT()
3943 DEFINE_TEST_NEON_2SAME_FP(fcvtms, Conversions) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
3997 DEFINE_TEST_NEON_2SAME_FP_SCALAR(fcvtms, Conversions) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
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| D | test-disasm-a64.cc | 2488 COMPARE(fcvtms(w0, s1), "fcvtms w0, s1"); in TEST()
2489 COMPARE(fcvtms(x2, s3), "fcvtms x2, s3"); in TEST()
2490 COMPARE(fcvtms(w4, d5), "fcvtms w4, d5"); in TEST()
2491 COMPARE(fcvtms(x6, d7), "fcvtms x6, d7"); in TEST()
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| D | test-assembler-a64.cc | 11156 TEST(fcvtms) { in TEST() argument
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| /external/v8/src/arm64/ |
| D | macro-assembler-arm64-inl.h | 618 fcvtms(rd, fn); in Fcvtms()
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| D | assembler-arm64.h | 1700 void fcvtms(const Register& rd, const FPRegister& fn);
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| D | assembler-arm64.cc | 2019 void Assembler::fcvtms(const Register& rd, const FPRegister& fn) { in fcvtms() function in v8::internal::Assembler
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| /external/vixl/src/vixl/a64/ |
| D | macro-assembler-a64.h | 1234 fcvtms(rd, vn); in Fcvtms()
2233 V(fcvtms, Fcvtms) \
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| D | assembler-a64.h | 2123 void fcvtms(const Register& rd, const VRegister& vn);
2129 void fcvtms(const VRegister& vd, const VRegister& vn);
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| D | assembler-a64.cc | 2832 V(fcvtms, NEON_FCVTMS, FCVTMS) \
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | basic-a64-instructions.txt | 1652 # CHECK: fcvtms w2, s3
1653 # CHECK: fcvtms x4, s5
1706 # CHECK: fcvtms w2, d3
1707 # CHECK: fcvtms x4, d5
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| D | neon-instructions.txt | 2561 # CHECK: fcvtms s22, s13
2562 # CHECK: fcvtms d21, d14
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| D | arm64-advsimd.txt | 472 # CHECK: fcvtms.2s v0, v0
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| /external/vixl/doc/ |
| D | supported-instructions.md | 1892 void fcvtms(const VRegister& vd, const VRegister& vn)
1899 void fcvtms(const Register& rd, const VRegister& vn)
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| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.stdout.exp | 26710 fcvtms d10, d21 18681caa09d8034ac0e161327f6b0c45 f8942473a90de53c4f21d965dc104153 0000000000000…
26712 fcvtms s10, s21 fea88f1cfbcb9c44261baab3b7c464ee f6bc1a1c97411fde476610efebad0456 0000000000000…
26714 fcvtms v10.2d, v21.2d f1bbf356235a0e8e6b39358bf5c9e677 6198636c1cf292b07d6ee9b05fd55119 7ffffff…
26716 fcvtms v10.4s, v21.4s 3a27fd64351d3fb2f03a63a93988289b ef079e50c961a9cdd980a8f73cea65c6 8000000…
26718 fcvtms v10.2s, v21.2s b9cf9a622125fc220836beec7ec87c5d 85d9821f0ac40979e945797022bf1865 0000000…
26720 fcvtms w21, s10 502a47fc6f46e986d48fd6f985127d94 4c950ba8ec1d70bd5f21d73e98445c2e 502a47fc6f46e…
26722 fcvtms x21, s10 b518a51db2c16ffa3e8cef1e52c7676b 41c3a69823b2cff1d28096033415e976 b518a51db2c16…
26724 fcvtms w21, d10 e89ab5c6ea988f7e452c0959e5e83be1 636652f0b18328144363b7c0f531c03e e89ab5c6ea988…
26726 fcvtms x21, d10 e8af77f618cb4910e97025ad3d75f9f6 b27b10af938f7b27b1c93974dc99e185 e8af77f618cb4…
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2337 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>;
2578 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>;
3089 defm FCVTMS : SIMDTwoScalarSD< 0, 0, 0b11011, "fcvtms">;
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