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Searched refs:fcvtmu (Results 1 – 25 of 27) sorted by relevance

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/external/llvm/test/CodeGen/AArch64/
Darm64-cvt.ll128 ;CHECK: fcvtmu w0, s0
130 %tmp3 = call i32 @llvm.aarch64.neon.fcvtmu.i32.f32(float %A)
136 ;CHECK: fcvtmu x0, s0
138 %tmp3 = call i64 @llvm.aarch64.neon.fcvtmu.i64.f32(float %A)
144 ;CHECK: fcvtmu w0, d0
146 %tmp3 = call i32 @llvm.aarch64.neon.fcvtmu.i32.f64(double %A)
152 ;CHECK: fcvtmu x0, d0
154 %tmp3 = call i64 @llvm.aarch64.neon.fcvtmu.i64.f64(double %A)
158 declare i32 @llvm.aarch64.neon.fcvtmu.i32.f32(float) nounwind readnone
159 declare i64 @llvm.aarch64.neon.fcvtmu.i64.f32(float) nounwind readnone
[all …]
Darm64-vcvt.ll99 ;CHECK: fcvtmu.2s v0, v0
101 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtmu.v2i32.v2f32(<2 x float> %A)
108 ;CHECK: fcvtmu.4s v0, v0
110 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtmu.v4i32.v4f32(<4 x float> %A)
117 ;CHECK: fcvtmu.2d v0, v0
119 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtmu.v2i64.v2f64(<2 x double> %A)
123 declare <2 x i32> @llvm.aarch64.neon.fcvtmu.v2i32.v2f32(<2 x float>) nounwind readnone
124 declare <4 x i32> @llvm.aarch64.neon.fcvtmu.v4i32.v4f32(<4 x float>) nounwind readnone
125 declare <2 x i64> @llvm.aarch64.neon.fcvtmu.v2i64.v2f64(<2 x double>) nounwind readnone
/external/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s112 fcvtmu s12, s13
113 fcvtmu d21, d14
Darm64-fp-encoding.s190 fcvtmu w1, s2
191 fcvtmu w1, d2
192 fcvtmu x1, s2
193 fcvtmu x1, d2
195 ; CHECK: fcvtmu w1, s2 ; encoding: [0x41,0x00,0x31,0x1e]
196 ; CHECK: fcvtmu w1, d2 ; encoding: [0x41,0x00,0x71,0x1e]
197 ; CHECK: fcvtmu x1, s2 ; encoding: [0x41,0x00,0x31,0x9e]
198 ; CHECK: fcvtmu x1, d2 ; encoding: [0x41,0x00,0x71,0x9e]
Dneon-simd-misc.s553 fcvtmu v6.4s, v8.4s
554 fcvtmu v6.2d, v8.2d
555 fcvtmu v4.2s, v0.2s
Darm64-advsimd.s675 fcvtmu.2s v0, v0
676 fcvtmu.4s v0, v0
677 fcvtmu.2d v0, v0
678 fcvtmu s0, s0
679 fcvtmu d0, d0 define
681 ; CHECK: fcvtmu.2s v0, v0 ; encoding: [0x00,0xb8,0x21,0x2e]
682 ; CHECK: fcvtmu.4s v0, v0 ; encoding: [0x00,0xb8,0x21,0x6e]
683 ; CHECK: fcvtmu.2d v0, v0 ; encoding: [0x00,0xb8,0x61,0x6e]
684 ; CHECK: fcvtmu s0, s0 ; encoding: [0x00,0xb8,0x21,0x7e]
685 ; CHECK: fcvtmu d0, d0 ; encoding: [0x00,0xb8,0x61,0x7e]
Dneon-diagnostics.s5916 fcvtmu v0.16b, v31.16b
5917 fcvtmu v2.8h, v4.8h
5918 fcvtmu v1.8b, v9.8b
5919 fcvtmu v13.4h, v21.4h
7222 fcvtmu s0, d0
7223 fcvtmu d0, s0 define
Dbasic-a64-instructions.s2075 fcvtmu w6, s7
2076 fcvtmu x8, s9
2129 fcvtmu w6, d7
2130 fcvtmu x8, d9
/external/valgrind/docs/internals/
DMERGE_3_10_1.txt92 //339927 Unhandled instruction 0x9E7100C6 (fcvtmu) on aarch64
/external/v8/test/cctest/
Dtest-disasm-arm64.cc1562 COMPARE(fcvtmu(w8, s9), "fcvtmu w8, s9"); in TEST_()
1563 COMPARE(fcvtmu(x10, s11), "fcvtmu x10, s11"); in TEST_()
1564 COMPARE(fcvtmu(w12, d13), "fcvtmu w12, d13"); in TEST_()
1565 COMPARE(fcvtmu(x14, d15), "fcvtmu x14, d15"); in TEST_()
/external/vixl/test/
Dtest-simulator-a64.cc2544 DEFINE_TEST_FP_TO_INT(fcvtmu, FPToU, Conversions) in DEFINE_TEST_FP_TO_INT()
3972 DEFINE_TEST_NEON_2SAME_FP(fcvtmu, Conversions) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
4018 DEFINE_TEST_NEON_2SAME_FP_SCALAR(fcvtmu, Conversions)
Dtest-disasm-a64.cc2492 COMPARE(fcvtmu(w8, s9), "fcvtmu w8, s9"); in TEST()
2493 COMPARE(fcvtmu(x10, s11), "fcvtmu x10, s11"); in TEST()
2494 COMPARE(fcvtmu(w12, d13), "fcvtmu w12, d13"); in TEST()
2495 COMPARE(fcvtmu(x14, d15), "fcvtmu x14, d15"); in TEST()
/external/v8/src/arm64/
Dmacro-assembler-arm64-inl.h625 fcvtmu(rd, fn); in Fcvtmu()
Dassembler-arm64.h1697 void fcvtmu(const Register& rd, const FPRegister& fn);
Dassembler-arm64.cc2014 void Assembler::fcvtmu(const Register& rd, const FPRegister& fn) { in fcvtmu() function in v8::internal::Assembler
/external/vixl/src/vixl/a64/
Dmacro-assembler-a64.h1240 fcvtmu(rd, vn); in Fcvtmu()
2234 V(fcvtmu, Fcvtmu) \
Dassembler-a64.h2126 void fcvtmu(const Register& rd, const VRegister& vn);
2132 void fcvtmu(const VRegister& vd, const VRegister& vn);
Dassembler-a64.cc2831 V(fcvtmu, NEON_FCVTMU, FCVTMU) \
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt1654 # CHECK: fcvtmu w6, s7
1655 # CHECK: fcvtmu x8, s9
1708 # CHECK: fcvtmu w6, d7
1709 # CHECK: fcvtmu x8, d9
Dneon-instructions.txt2570 # CHECK: fcvtmu s12, s13
2571 # CHECK: fcvtmu d21, d14
Darm64-advsimd.txt473 # CHECK: fcvtmu.2s v0, v0
/external/vixl/doc/
Dsupported-instructions.md1906 void fcvtmu(const VRegister& vd, const VRegister& vn)
1913 void fcvtmu(const Register& rd, const VRegister& vn)
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp26711 fcvtmu d21, d10 999d077a4bae058dc7320df8ca32636e 39c16542dd488bf7537b9093873da1cd 0000000000000…
26713 fcvtmu s21, s10 a6671370780f2a4f3d7e9744a50170a7 8e64a5df37da01d28ac2b858683fcad0 0000000000000…
26715 fcvtmu v10.2d, v21.2d d039b6a3a668315b7f4c02d52f4dfc12 27cb13aa8951e8788df30e95d513e126 0000000…
26717 fcvtmu v10.4s, v21.4s ff42988f2af21b9531196d0adc663794 aa68569887088f658df7c31f54db238e 0000000…
26719 fcvtmu v10.2s, v21.2s 7b1aca8ef99a4fe2aa1efa401990cf15 9358b427a019edcd94f3ec8869e8e109 0000000…
26721 fcvtmu w21, s10 99de708ce10829eee569b2f8232fe5bc 116de6834db0f029a9b09a7112b3e9b2 99de708ce1082…
26723 fcvtmu x21, s10 05b647913f511c8a3ed7ec4973ba6482 3c76aac7cf036df53b712ad2604abc5a 05b647913f511…
26725 fcvtmu w21, d10 bea2509d127629b5b369a73008314d68 1572fff3271262304b359cab54ac5702 bea2509d12762…
26727 fcvtmu x21, d10 c5a18ab15b774f70471fe4afe3939f6d 9b62e50654dbd2dad8fdeffbeed9bda9 c5a18ab15b774…
/external/valgrind/
DNEWS163 343332 Unhandled instruction 0x9E310021 (fcvtmu) on aarch64
260 339927 Unhandled instruction 0x9E7100C6 (fcvtmu) on aarch64
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2338 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>;
2579 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>;
3090 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;

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