Searched refs:fmulx (Results 1 – 22 of 22) sorted by relevance
64 declare float @llvm.aarch64.neon.fmulx.f32(float, float)68 ; CHECK: fmulx {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]70 %tmp2 = call float @llvm.aarch64.neon.fmulx.f32(float %a, float %tmp1)76 ; CHECK: fmulx {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]78 %tmp2 = call float @llvm.aarch64.neon.fmulx.f32(float %a, float %tmp1)84 ; CHECK: fmulx {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]86 %tmp2 = call float @llvm.aarch64.neon.fmulx.f32(float %tmp1, float %a)90 declare double @llvm.aarch64.neon.fmulx.f64(double, double)94 ; CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+.d\[0]|d[0-9]+}}96 %tmp2 = call double @llvm.aarch64.neon.fmulx.f64(double %a, double %tmp1)[all …]
225 ;CHECK: fmulx.2s228 %tmp3 = call <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)234 ;CHECK: fmulx.4s237 %tmp3 = call <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)243 ;CHECK: fmulx.2d246 %tmp3 = call <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)250 declare <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float>, <2 x float>) nounwind readnone251 declare <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float>, <4 x float>) nounwind readnone252 declare <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double>, <2 x double>) nounwind readnone716 ;CHECK: fmulx.2s[all …]
770 declare <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float>, <2 x float>)771 declare <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float>, <4 x float>)772 declare <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double>, <2 x double>)777 ; CHECK: fmulx v0.2s, v0.2s, v1.2s778 %val = call <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float> %lhs, <2 x float> %rhs)785 ; CHECK: fmulx v0.4s, v0.4s, v1.4s786 %val = call <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float> %lhs, <4 x float> %rhs)793 ; CHECK: fmulx v0.2d, v0.2d, v1.2d794 … %val = call <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double> %lhs, <2 x double> %rhs)
3 declare <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double>, <2 x double>)5 declare <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float>, <4 x float>)7 declare <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float>, <2 x float>)1444 …%vmulx2.i = tail call <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float> %a, <2 x float> %shuf…1454 …%vmulx2.i = tail call <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float> %a, <4 x float> %shuf…1464 …%vmulx2.i = tail call <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double> %a, <2 x double> %s…1474 …%vmulx2.i = tail call <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float> %a, <2 x float> %shuf…1484 …%vmulx2.i = tail call <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float> %a, <4 x float> %shuf…1494 …%vmulx2.i = tail call <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double> %a, <2 x double> %s…2800 …%vmulx2.i = tail call <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float> %a, <2 x float> %shuf…[all …]
24 fmulx s6, s2, v8.s[0]25 fmulx s7, s3, v13.s[1]26 fmulx s9, s7, v9.s[2]27 fmulx s13, s21, v10.s[3]28 fmulx d15, d9, v7.d[0]29 fmulx d13, d12, v11.d[1]
79 fmulx v21.2s, v5.2s, v13.2s80 fmulx v1.4s, v25.4s, v3.4s81 fmulx v31.2d, v22.2d, v2.2d
29 fmulx s20, s22, s1530 fmulx d23, d11, d1
189 fmulx v0.2s, v1.2s, v2.s[2]190 fmulx v0.2s, v1.2s, v22.s[2]191 fmulx v0.4s, v1.4s, v2.s[2]192 fmulx v0.4s, v1.4s, v22.s[2]193 fmulx v0.2d, v1.2d, v2.d[1]194 fmulx v0.2d, v1.2d, v22.d[1]
1280 fmulx v21.2s, v5.2s, v13.2d1281 fmulx v1.4h, v25.4h, v3.4h3453 fmulx v0.4h, v1.4h, v2.h[4]3454 fmulx v0.2s, v1.2s, v2.s[4]3455 fmulx v0.2s, v1.2s, v22.s[4]3456 fmulx v0.4s, v1.4s, v2.s[4]3457 fmulx v0.4s, v1.4s, v22.s[4]3458 fmulx v0.2d, v1.2d, v2.d[2]3459 fmulx v0.2d, v1.2d, v22.d[2]3875 fmulx s20, h22, s15[all …]
327 fmulx.2s v0, v0, v0329 fmulx d2, d3, d1 define330 fmulx s2, s3, s1397 ; CHECK: fmulx.2s v0, v0, v0 ; encoding: [0x00,0xdc,0x20,0x0e]400 ; CHECK: fmulx d2, d3, d1 ; encoding: [0x62,0xdc,0x61,0x5e]401 ; CHECK: fmulx s2, s3, s1 ; encoding: [0x62,0xdc,0x21,0x5e]987 fmulx.s s0, s0, v0[3]988 fmulx.d d0, d0, v0[1]1005 ; CHECK: fmulx.s s0, s0, v0[3] ; encoding: [0x00,0x98,0xa0,0x7f]1006 ; CHECK: fmulx.d d0, d0, v0[1] ; encoding: [0x00,0x98,0xc0,0x7f][all …]
669 # CHECK: fmulx v1.2s, v22.2s, v2.2s670 # CHECK: fmulx v21.4s, v15.4s, v3.4s671 # CHECK: fmulx v11.2d, v5.2d, v23.2d1491 # CHECK: fmulx s20, s22, s151492 # CHECK: fmulx d23, d11, d12297 # CHECK: fmulx s3, s5, v7.s[0]2298 # CHECK: fmulx s3, s5, v7.s[3]2299 # CHECK: fmulx s3, s5, v15.s[3]2300 # CHECK: fmulx d0, d4, v8.d[0]2301 # CHECK: fmulx d0, d4, v8.d[1]
312 # CHECK: fmulx.2s v0, v0, v01603 # CHECK: fmulx.s s0, s0, v0[3]1604 # CHECK: fmulx.d d0, d0, v0[1]1696 # CHECK: fmulx.2s v0, v0, v0[0]1697 # CHECK: fmulx.4s v0, v0, v0[1]1698 # CHECK: fmulx.2d v0, v0, v0[1]2313 # CHECK: fmulx s2, s3, s12315 # CHECK: fmulx d2, d3, d1
3728 DEFINE_TEST_NEON_3SAME_FP(fmulx, Basic)3793 DEFINE_TEST_NEON_3SAME_FP_SCALAR(fmulx, Basic)4069 DEFINE_TEST_NEON_FP_BYELEMENT(fmulx, Basic, Basic, Basic)4081 DEFINE_TEST_NEON_FP_BYELEMENT_SCALAR(fmulx, Basic, Basic, Basic)
2657 case NEON_FMULX: fmulx(vf, rd, rn, rm); break; in VisitNEON3Same()2947 case NEON_FMULX_byelement: Op = &Simulator::fmulx; break; in VisitNEONByIndexedElement()3553 case NEON_FMULX_scalar: fmulx(vf, rd, rn, rm); break; in VisitNEONScalar3Same()3654 case NEON_FMULX_byelement_scalar: Op = &Simulator::fmulx; break; in VisitNEONScalarByIndexedElement()
1610 LogicVRegister fmulx(VectorFormat vform,2312 V(fmulx, FPMulx, true) \
2111 V(fmulx, Fmulx) \2330 V(fmulx, Fmulx) \
3526 void fmulx(const VRegister& vd,3559 void fmulx(const VRegister& vd,
4332 LogicVRegister Simulator::fmulx(VectorFormat vform, in fmulx() function in vixl::Simulator4341 fmulx<float>(vform, dst, src1, index_reg); in fmulx()4346 fmulx<double>(vform, dst, src1, index_reg); in fmulx()
3244 V(fmulx, NEON_FMULX, NEON_FMULX_scalar) \3515 V(fmulx, NEON_FMULX_byelement)
26604 fmulx d2, d11, v29.d[0] 3e3dde3c658765b3b58a5ad0ef974f8a 8b8683df768bf0f5b05b0ea749bc778f 6b745…26605 fmulx d2, d11, v29.d[1] c98362f719b366b4200c7f16d790dfcf 67fa6ac327e9aa358865657492a79797 9254b…26606 fmulx s2, s11, v29.s[0] d5723845e469ca15d2f0f3c04d3b0133 5b45c938261e8df27d3e71e3ded34f1d e6b93…26607 fmulx s2, s11, v29.s[3] 669ec3998cfcb7084e499ac2936d586c 6bfc04b1377ebf5f13fc17e7711443d5 6d362…26608 fmulx v2.2d, v11.2d, v29.d[0] 9ab17fa31f5e64b1cdb13974903c1672 29611011b9edb14c5f4c5a9ef4a9cf53 …26609 fmulx v2.2d, v11.2d, v29.d[1] 1ecc3ac47977bdd260ea993c6486ae8b 3ae6e0f3edb1bd641115f5e788e973a8 …26610 fmulx v2.4s, v11.4s, v29.s[0] 510d13564df5ca42e396020adc013bee def53c4ede01a3b222e9b1db82f7b06f …26611 fmulx v2.4s, v11.4s, v29.s[3] c6b6fd3af9befbd16e647afaa2ef1931 5b9bd0f9dee9733e104de1303e054573 …26613 fmulx v2.2s, v11.2s, v29.s[0] b36cff69b0bc51395e556bdb02e8d569 14483a5ab44897f7ee2a705335793790 …26614 fmulx v2.2s, v11.2s, v29.s[3] ebfb2e1117ce62da901532ce11730405 f8edf0fac50254b489792cbcf08e8aee …[all …]
2291 void fmulx(const VRegister& vd,2301 void fmulx(const VRegister& vd,
2749 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_aarch64_neon_fmulx>;2997 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_aarch64_neon_fmulx>;4326 defm FMULX : SIMDFPIndexedSD<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>;