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Searched refs:getRegClassFor (Results 1 – 23 of 23) sorted by relevance

/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp98 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValPredInSU()
136 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValSuccInSU()
336 && TLI->getRegClassFor(VT) in rawRegPressureDelta()
337 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
347 if (TLI->isTypeLegal(VT) && TLI->getRegClassFor(VT) in rawRegPressureDelta()
348 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
489 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode()
500 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode()
DInstrEmitter.cpp108 UseRC = TLI->getRegClassFor(VT); in EmitCopyFromReg()
166 DstRC = TLI->getRegClassFor(VT); in EmitCopyFromReg()
228 TLI->getRegClassFor(Node->getSimpleValueType(i)); in CreateVirtualRegisters()
293 TLI->getRegClassFor(Op.getSimpleValueType()); in getVR()
456 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); in ConstrainForSubReg()
491 TLI->getRegClassFor(Node->getSimpleValueType(0)); in EmitSubregNode()
546 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0)); in EmitSubregNode()
DFastISel.cpp254 Reg = createResultReg(TLI.getRegClassFor(VT)); in materializeConstant()
743 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64)); in selectPatchpoint()
1287 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT); in selectBitCast()
1288 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT); in selectBitCast()
1953 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in fastEmitInst_extractsubreg()
DFunctionLoweringInfo.cpp475 MF->getSubtarget().getTargetLowering()->getRegClassFor(VT)); in CreateReg()
DSelectionDAGBuilder.cpp2090 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy()); in visitLandingPadClauseBB()
5157 TLI.getRegClassFor(Src.getSimpleValueType()); in visitIntrinsicCall()
6631 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT)) in visitInlineAsm()
7603 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT)); in LowerArguments()
DSelectionDAGISel.cpp917 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy()); in PrepareEHLandingPad()
DDAGCombiner.cpp9380 const TargetRegisterClass *ResRC = TLI.getRegClassFor(ResVT.getSimpleVT()); in canMergeExpensiveCrossRegisterBankCopy()
9382 TLI.getRegClassFor(Use->getOperand(0).getValueType().getSimpleVT()); in canMergeExpensiveCrossRegisterBankCopy()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp448 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToFPReg()
458 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToIntReg()
484 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
500 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
565 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeInt()
655 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
669 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
720 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); in fastMaterializeAlloca()
1027 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
1038 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
[all …]
DARMISelLowering.h358 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
DARMISelLowering.cpp1148 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const { in getRegClassFor() function in ARMTargetLowering
1158 return TargetLowering::getRegClassFor(VT); in getRegClassFor()
3970 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32)); in LowerRETURNADDR()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp1749 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitCMoveSelect()
1925 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitSSESelect()
2013 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitPseudoSelect()
2041 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86SelectSelect()
2256 const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::v8i16); in fastLowerIntrinsicCall()
2551 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
2584 TLI.getRegClassFor(VT), RHSReg, RHSIsKill); in fastLowerIntrinsicCall()
2594 ResultReg = fastEmitInst_r(MULOpc[0], TLI.getRegClassFor(VT), RHSReg, in fastLowerIntrinsicCall()
2598 TLI.getRegClassFor(VT), LHSReg, LHSIsKill, in fastLowerIntrinsicCall()
2672 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
[all …]
DX86ISelLowering.cpp2401 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy)); in LowerFormalArguments()
2580 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT)); in LowerFormalArguments()
10439 const TargetRegisterClass* rc = getRegClassFor(VecVT); in ExtractBitFromMaskVector()
10441 rc = getRegClassFor(MVT::v16i1); in ExtractBitFromMaskVector()
10591 const TargetRegisterClass* rc = getRegClassFor(VecVT); in InsertBitToMaskVector()
14345 getRegClassFor(getPointerTy()); in LowerDYNAMIC_STACKALLOC()
18068 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); in EmitVAARG64WithCustomInserter()
18069 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); in EmitVAARG64WithCustomInserter()
18625 getRegClassFor(getPointerTy()); in EmitLoweredSegAlloca()
18865 const TargetRegisterClass *PtrRC = getRegClassFor(PVT); in emitEHSjLjSetJmp()
/external/llvm/lib/CodeGen/
DCallingConvLower.cpp243 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters()
DMachineScheduler.cpp2407 TLI->getRegClassFor(LegalIntVT)); in initPolicy()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp1032 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); in emitAtomicBinary()
1131 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitSignExtendToI32InReg()
1151 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitAtomicBinaryPartword()
1303 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); in emitAtomicCmpSwap()
1385 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitAtomicCmpSwapPartword()
2006 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); in lowerRETURNADDR()
2952 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
3019 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); in LowerFormalArguments()
3336 RC = getRegClassFor(VT); in parseRegForInlineAsmConstraint()
3345 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); in parseRegForInlineAsmConstraint()
[all …]
DMipsSEISelDAGToDAG.cpp926 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple); in selectNode()
DMipsFastISel.cpp1093 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); in finishCall()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp370 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm); in materializeFP()
383 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
403 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
491 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true); in fastMaterializeFloatZero()
2811 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg, in selectIntToFP()
3043 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); in finishCall()
3478 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
3638 ResultReg1 = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp1389 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT); in finishCall()
1398 ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in finishCall()
1875 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in PPCMaterializeFP()
DPPCISelLowering.cpp8119 const TargetRegisterClass *PtrRC = getRegClassFor(PVT); in emitEHSjLjSetJmp()
/external/llvm/include/llvm/Target/
DTargetLowering.h364 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const { in getRegClassFor() function
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp567 getRegClassFor(VA.getLocVT())); in LowerFormalArguments_64()
2498 TLI.getRegClassFor(TLI.getPointerTy())); in LowerRETURNADDR()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1183 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32)); in LowerRETURNADDR()