| /external/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.h | 115 bool isVector() const { in isVector() function
116 return isSimple() ? V.isVector() : isExtendedVector(); in isVector()
211 return isVector() ? getVectorElementType() : *this; in getScalarType()
217 assert(isVector() && "Invalid vector type!"); in getVectorElementType()
226 assert(isVector() && "Invalid vector type!"); in getVectorNumElements()
259 assert(isInteger() && !isVector() && "Invalid integer type!"); in getRoundIntegerType()
271 assert(isInteger() && !isVector() && "Invalid integer type!"); in getHalfSizedIntegerVT()
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| D | SelectionDAG.h | 705 assert(LHS.getValueType().isVector() == RHS.getValueType().isVector() &&
707 assert(LHS.getValueType().isVector() == VT.isVector() &&
720 assert(VT.isVector() == LHS.getValueType().isVector() &&
722 return getNode(Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT, DL, VT,
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| D | MachineValueType.h | 197 bool isVector() const { in isVector() function
277 return isVector() ? getVectorElementType() : *this; in getScalarType()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILPeepholeOptimizer.cpp | 471 bool isVector = aType->isVectorTy(); in optimizeBitInsert() local
478 if (isVector) { in optimizeBitInsert()
488 if (isVector) { in optimizeBitInsert()
659 if (isVector) { name += "_v" + itostr(numEle) + "u32"; } else { name += "_u32"; } in optimizeBitInsert()
711 bool isVector = aType->isVectorTy(); in optimizeBitExtract() local
714 if (isVector) { in optimizeBitExtract()
723 if (isVector) { in optimizeBitExtract()
751 if (isVector) { in optimizeBitExtract()
819 if (isVector) { in optimizeBitExtract()
1007 bool isVector = aType->isVectorTy(); in expandSigned24BitOps() local
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| D | R600InstrInfo.h | 55 bool isVector(const MachineInstr &MI) const;
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| D | R600ExpandSpecialInstrs.cpp | 64 bool IsVector = TII->isVector(MI); in runOnMachineFunction()
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| /external/llvm/utils/TableGen/ |
| D | DAGISelEmitter.cpp | 88 if (LHSVT.isVector() != RHSVT.isVector()) in operator ()()
89 return RHSVT.isVector(); in operator ()()
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| D | CodeGenDAGPatterns.cpp | 40 static inline bool isVector(MVT::SimpleValueType VT) { in isVector() function
41 return MVT(VT).isVector(); in isVector()
44 return !MVT(VT).isVector(); in isScalar()
137 if (isVector(TypeVec[i])) in hasVectorTypes()
330 return FillWithPossibleTypes(TP, isVector, "vector"); in EnforceVector()
337 if (!isVector(TypeVec[i])) { in EnforceVector()
412 if (OtherVT.isVector() != Smallest.isVector()) in EnforceSmallerThan()
439 if (OtherVT.isVector() != Largest.isVector()) in EnforceSmallerThan()
471 assert(isVector(TypeVec[i]) && "EnforceVector didn't work"); in EnforceVectorEltTypeIs()
518 assert(isVector(TypeVec[i]) && "EnforceVector didn't work"); in EnforceVectorEltTypeIs()
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| D | DAGISelMatcher.cpp | 371 return !MVT(T2).isInteger() || MVT(T2).isVector(); in TypesAreContradictory()
374 return !MVT(T1).isInteger() || MVT(T1).isVector(); in TypesAreContradictory()
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| /external/clang/utils/ABITest/ |
| D | TypeGen.py | 117 def __init__(self, index, isVector, elementType, size): argument
118 if isVector:
124 self.isVector = isVector
127 if isVector:
135 if self.isVector:
144 if self.isVector:
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 142 HasVectors |= J->isVector(); in Run()
202 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) in LegalizeOp()
232 if (StVT.isVector() && ST->isTruncatingStore()) in LegalizeOp()
252 HasVectorValue |= J->isVector(); in LegalizeOp()
393 if (Op.getOperand(j).getValueType().isVector()) in Promote()
398 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint()) in Promote()
408 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() && in Promote()
409 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint())) in Promote()
438 if (Op.getOperand(j).getValueType().isVector()) in PromoteINT_TO_FP()
714 assert(VT.isVector() && !Mask.getValueType().isVector() in ExpandSELECT()
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| D | LegalizeVectorTypes.cpp | 344 assert(N->getValueType(0).isVector() == in ScalarizeVecRes_SETCC()
345 N->getOperand(0).getValueType().isVector() && in ScalarizeVecRes_SETCC()
348 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N); in ScalarizeVecRes_SETCC()
372 assert(N->getValueType(0).isVector() && in ScalarizeVecRes_VSETCC()
373 N->getOperand(0).getValueType().isVector() && in ScalarizeVecRes_VSETCC()
1048 assert(N->getValueType(0).isVector() && in SplitVecRes_SETCC()
1049 N->getOperand(0).getValueType().isVector() && in SplitVecRes_SETCC()
1362 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?"); in SplitVecOp_VSELECT()
1661 assert(N->getValueType(0).isVector() && in SplitVecOp_VSETCC()
1662 N->getOperand(0).getValueType().isVector() && in SplitVecOp_VSETCC()
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| D | SelectionDAG.cpp | 739 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && in VerifySDNode()
752 assert(N->getValueType(0).isVector() && "Wrong return type!"); in VerifySDNode()
1025 assert(!VT.isVector() && in getZeroExtendInReg()
1037 assert(VT.isVector() && "This DAG node is restricted to vector types."); in getAnyExtendVectorInReg()
1047 assert(VT.isVector() && "This DAG node is restricted to vector types."); in getSignExtendVectorInReg()
1057 assert(VT.isVector() && "This DAG node is restricted to vector types."); in getZeroExtendVectorInReg()
1115 if (VT.isVector() && TLI->getTypeAction(*getContext(), EltVT) == in getConstant()
1127 else if (NewNodesMustHaveLegalTypes && VT.isVector() && in getConstant()
1180 if (!VT.isVector()) in getConstant()
1190 if (VT.isVector()) { in getConstant()
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| D | DAGCombiner.cpp | 423 if (LHSTy.isVector()) in getShiftAmountTy()
982 if (VT.isVector() || !VT.isInteger()) in PromoteIntBinOp()
1040 if (VT.isVector() || !VT.isInteger()) in PromoteIntShiftOp()
1084 if (VT.isVector() || !VT.isInteger()) in PromoteExtend()
1113 if (VT.isVector() || !VT.isInteger()) in PromoteLoad()
1581 if (VT.isVector()) { in visitADD()
1670 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) in visitADD()
1674 if (VT.isInteger() && !VT.isVector()) { in visitADD()
1813 if (!VT.isVector()) in tryFoldToZero()
1826 if (VT.isVector()) { in visitSUB()
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| D | LegalizeIntegerTypes.cpp | 247 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector()) in PromoteIntRes_BITCAST()
269 if (!NOutVT.isVector()) in PromoteIntRes_BITCAST()
294 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector()) in PromoteIntRes_BITCAST()
577 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() && in PromoteIntRes_SETCC()
584 !LHS.getValueType().isVector()) in PromoteIntRes_SETCC()
587 !RHS.getValueType().isVector()) in PromoteIntRes_SETCC()
603 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt; in PromoteIntRes_SHL()
627 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt; in PromoteIntRes_SRA()
635 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt; in PromoteIntRes_SRL()
656 assert(InVT.isVector() && "Cannot split scalar types"); in PromoteIntRes_TRUNCATE()
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| D | LegalizeTypesGeneric.cpp | 99 if (InVT.isVector() && OutVT.isInteger()) { in ExpandRes_BITCAST()
339 if (N->getValueType(0).isVector()) { in ExpandOp_BITCAST()
525 if (Cond.getValueType().isVector()) { in SplitRes_SELECT()
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| /external/clang/include/clang/AST/ |
| D | APValue.h | 187 bool isVector() const { return Kind == Vector; } in isVector() function
259 assert(isVector() && "Invalid accessor"); in getVectorElt()
267 assert(isVector() && "Invalid accessor"); in getVectorLength()
356 assert(isVector() && "Invalid accessor"); in setVector()
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMELFStreamer.cpp | 141 bool isVector) override;
205 bool isVector) { in emitRegSave() argument
207 if (isVector) in emitRegSave()
431 bool isVector) override;
496 void emitRegSave(const SmallVectorImpl<unsigned> &RegList, bool isVector);
713 bool isVector) { in emitRegSave() argument
714 getStreamer().emitRegSave(RegList, isVector); in emitRegSave()
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| D | ARMTargetStreamer.cpp | 54 bool isVector) {} in emitRegSave() argument
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| /external/llvm/lib/Target/R600/ |
| D | R600EmitClauseMarkers.cpp | 59 if(TII->isVector(*MI) || in OccupiedDwords()
77 if (TII->isVector(*MI) || TII->isCubeOp(MI->getOpcode())) in isALU()
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| D | CaymanInstructions.td | 32 let isVector = 1 in {
47 } // End isVector = 1
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| D | R600ISelLowering.cpp | 1393 if (ValueVT.isVector()) { in LowerSTORE()
1498 if (LoadNode->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS && VT.isVector()) { in LowerLOAD()
1527 if (VT.isVector()) { in LowerLOAD()
1542 if (!VT.isVector()) { in LowerLOAD()
1563 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8)); in LowerLOAD()
1591 if (VT.isVector()) { in LowerLOAD()
1665 if (!VT.isVector() && MemVT.isVector()) { in LowerFormalArguments()
1719 if (!VT.isVector()) in getSetCCResultType()
2083 if (ParentNode->getValueType(0).isVector()) in FoldOperand()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AsmPrinter.cpp | 94 const TargetRegisterClass *RC, bool isVector,
239 bool isVector, raw_ostream &O) { in printAsmRegInClass() argument
247 RegToPrint, isVector ? AArch64::vreg : AArch64::NoRegAltName); in printAsmRegInClass()
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| /external/clang/utils/TableGen/ |
| D | NeonEmitter.cpp | 170 bool isVector() const { return NumVectors > 0; } in isVector() function in __anon67a52ed10111::Type
201 assert(isVector()); in makeOneVector()
557 if (isVector()) in str()
1015 if (T.isHalf() && T.isVector() && !T.isScalarForMangling()) in getBuiltinTypeStr()
1211 if (!NewV.getType().isVector() || NewV.getType().getNumElements() == 1) in emitArgumentReversal()
1223 if (!getReturnType().isVector() || getReturnType().isVoid() || in emitReturnReversal()
1338 if (CastToType.isVector()) { in emitBodyAsBuiltinCall()
1675 assert_with_loc(T.isVector(), "dup() used but default type is scalar!"); in emitDagDup()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 60 unsigned matchRegisterNameAlias(StringRef Name, bool isVector);
174 bool isVector; member
866 bool isReg() const override { return Kind == k_Register && !Reg.isVector; } in isReg()
867 bool isVectorReg() const { return Kind == k_Register && Reg.isVector; } in isVectorReg()
869 return Kind == k_Register && Reg.isVector && in isVectorRegLo()
874 return Kind == k_Register && !Reg.isVector && in isGPR32as64()
879 return Kind == k_Register && !Reg.isVector && in isGPR64sp0()
1542 CreateReg(unsigned RegNum, bool isVector, SMLoc S, SMLoc E, MCContext &Ctx) { in CreateReg() argument
1545 Op->Reg.isVector = isVector; in CreateReg()
1840 bool isVector) { in matchRegisterNameAlias() argument
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