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Searched refs:memd (Results 1 – 14 of 14) sorted by relevance

/external/llvm/test/MC/Disassembler/Hexagon/
Dst.txt6 # CHECK: memd(r17 + r21<<#3) = r31:30
8 # CHECK: memd(##320) = r21:20
10 # CHECK: memd(r17+#168) = r21:20
12 # CHECK: memd(r17 ++ I:circ(m1)) = r21:20
14 # CHECK: memd(r17 ++ #40:circ(m1)) = r21:20
16 # CHECK: memd(r17++#40) = r21:20
18 # CHECK: memd(r17++m1) = r21:20
20 # CHECK: memd(r17 ++ m1:brev) = r21:20
24 # CHECK: if (p3) memd(r17+r21<<#3) = r31:30
26 # CHECK: if (!p3) memd(r17+r21<<#3) = r31:30
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Dld.txt6 # CHECK: r17:16 = memd(r21 + r31<<#3)
8 # CHECK: r17:16 = memd(##320)
10 # CHECK: r17:16 = memd(r21 ++ #40:circ(m1))
12 # CHECK: r17:16 = memd(r21 ++ I:circ(m1))
14 # CHECK: r17:16 = memd(r21++#40)
16 # CHECK: r17:16 = memd(r21++m1)
18 # CHECK: r17:16 = memd(r21 ++ m1:brev)
22 # CHECK: if (p3) r17:16 = memd(r21+r31<<#3)
24 # CHECK: if (!p3) r17:16 = memd(r21+r31<<#3)
27 # CHECK-NEXT: if (p3.new) r17:16 = memd(r21+r31<<#3)
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/external/llvm/test/CodeGen/Hexagon/
Dzextloadi1.ll5 ; CHECK: memd(##i129_s) = r{{[0-9]+:[0-9]+}}
8 ; CHECK: memd(##i65_s) = r{{[0-9]+:[0-9]+}}
Dsimpletailcall.ll4 ; CHECK-NOT: memd(r29
Dcirc_st.ll10 ; memd(r1++#-8:circ(m0)) = r1:0
44 ; CHECK: memd(r{{[0-9]*}}{{.}}++{{.}}#-8:circ(m{{[0-1]}}))
Dbrev_st.ll10 ; memd(r0++m0:brev) = r1:0
29 ; CHECK: memd(r{{[0-9]*}} ++ m{{[0-1]}}:brev)
Dabsaddr-store.ll41 ; CHECK: memd(##d){{ *}}={{ *}}r{{[0-9]+}}:{{[0-9]+}}
Dbrev_ld.ll11 ; r3:2 = memd(r0++m0:brev)
32 ; CHECK: memd(r{{[0-9]*}} ++ m{{[0-1]}}:brev)
Dcirc_ld.ll11 ; r3:2 = memd(r1++#-8:circ(m0))
48 ; CHECK: memd(r{{[0-9]*.}}++{{.}}#-8:circ(m{{[0-1]}}))
Didxload-with-zero-offset.ll64 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}memd(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#…
/external/valgrind/VEX/test/
Dmmxtest.c137 #define mmx_m2m(op, mems, memd) \ argument
142 mmx_trace = (memd); \
143 fprintf(stderr, #memd "=0x%016llx) => ", mmx_trace.q); \
147 : "=X" (memd) \
149 mmx_trace = (memd); \
150 fprintf(stderr, #memd "=0x%016llx\n", mmx_trace.q); \
171 #define mmx_m2m(op, mems, memd) \ argument
175 : "=X" (memd) \
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoV4.td436 def L4_loadrd_ap : T_LD_abs_set <"memd", DoubleRegs, 0b1110>;
494 def L4_loadrd_ur : T_LoadAbsReg<"memd", "LDrid", DoubleRegs, 0b1110>;
615 defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>;
704 def S4_storerd_ap : T_ST_absset <"memd", "STrid", DoubleRegs,
773 def S4_storerd_ur : T_StoreAbsReg <"memd", "STrid", DoubleRegs, 0b110,
1006 defm storerd: ST_Idxd_shl<"memd", "STrid", DoubleRegs, 0b110>;
1024 // memd(Rx++#s4:3)=Rtt
1025 // memd(Rx++#s4:3:circ(Mu))=Rtt
1026 // memd(Rx++I:circ(Mu))=Rtt
1027 // memd(Rx++Mu)=Rtt
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DHexagonInstrInfo.td1728 defm loadrd: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, 0b1110>;
1925 defm loadrd : LD_PostInc <"memd", "LDrid", DoubleRegs, s4_3Imm, 0b1110>;
2009 def L2_loadrd_pr : T_load_pr <"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
2075 def L2_loadrd_pcr : T_load_pcr <"memd", DoubleRegs, 0b1110>;
2161 def L2_loadrd_pci : T_load_pci <"memd", DoubleRegs, s4_3Imm, 0b1110>;
2183 def L2_loadrd_pci_pseudo : T_load_pci_pseudo <"memd", DoubleRegs>;
2279 def L2_loadrd_pbr : T_load_pbr <"memd", DoubleRegs, DoubleWordAccess, 0b1110>;
2303 def L2_loadrd_pbr_pseudo : T_load_pbr_pseudo <"memd", DoubleRegs>;
3389 defm storerd: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm, 0b1110>;
3432 def S2_storerd_pr : T_store_pr<"memd", DoubleRegs, 0b110, DoubleWordAccess>;
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DHexagonInstrFormats.td59 def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd)