/external/llvm/test/MC/AArch64/ |
D | trace-regs.s | 3 mrs x8, trcstatr 4 mrs x9, trcidr8 5 mrs x11, trcidr9 6 mrs x25, trcidr10 7 mrs x7, trcidr11 8 mrs x7, trcidr12 9 mrs x6, trcidr13 10 mrs x27, trcidr0 11 mrs x29, trcidr1 12 mrs x4, trcidr2 [all …]
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D | arm64-system-encoding.s | 221 mrs x3, ACTLR_EL1 222 mrs x3, ACTLR_EL2 223 mrs x3, ACTLR_EL3 224 mrs x3, AFSR0_EL1 225 mrs x3, AFSR0_EL2 226 mrs x3, AFSR0_EL3 227 mrs x3, AIDR_EL1 228 mrs x3, AFSR1_EL1 229 mrs x3, AFSR1_EL2 230 mrs x3, AFSR1_EL3 [all …]
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D | gicv3-regs.s | 3 mrs x8, icc_iar1_el1 4 mrs x26, icc_iar0_el1 5 mrs x2, icc_hppir1_el1 6 mrs x17, icc_hppir0_el1 7 mrs x29, icc_rpr_el1 8 mrs x4, ich_vtr_el2 9 mrs x24, ich_eisr_el2 10 mrs x9, ich_elsr_el2 11 mrs x24, icc_bpr1_el1 12 mrs x14, icc_bpr0_el1 [all …]
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D | basic-a64-instructions.s | 4198 mrs x9, TEECR32_EL1 4199 mrs x9, OSDTRRX_EL1 4200 mrs x9, MDCCSR_EL0 4201 mrs x9, MDCCINT_EL1 4202 mrs x9, MDSCR_EL1 4203 mrs x9, OSDTRTX_EL1 4204 mrs x9, DBGDTR_EL0 4205 mrs x9, DBGDTRRX_EL0 4206 mrs x9, OSECCR_EL1 4207 mrs x9, DBGVCR32_EL2 [all …]
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D | gicv3-regs-diagnostics.s | 4 mrs x10, icc_eoir1_el1 5 mrs x7, icc_eoir0_el1 6 mrs x22, icc_dir_el1 7 mrs x24, icc_sgi1r_el1 8 mrs x8, icc_asgi1r_el1 9 mrs x28, icc_sgi0r_el1
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D | arm64-spsel-sysreg.s | 8 mrs x0, SPSel label 9 mrs x0, ESR_EL1 label 21 mrs x0, DAIFSet label
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D | armv8.1a-pan.s | 12 mrs x13, pan 18 mrs w0, pan
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D | trace-regs-diagnostics.s | 3 mrs x12, trcoslar 4 mrs x10, trclar
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D | armv8.1a-lor.s | 28 mrs x0, LORID_EL1
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/external/llvm/test/MC/ARM/ |
D | move-banked-regs.s | 4 mrs r2, r8_usr 5 mrs r3, r9_usr 6 mrs r5, r10_usr 7 mrs r7, r11_usr 8 mrs r11, r12_usr 9 mrs r1, sp_usr 10 mrs r2, lr_usr 11 @ CHECK-ARM: mrs r2, r8_usr @ encoding: [0x00,0x22,0x00,0xe1] 12 @ CHECK-ARM: mrs r3, r9_usr @ encoding: [0x00,0x32,0x01,0xe1] 13 @ CHECK-ARM: mrs r5, r10_usr @ encoding: [0x00,0x52,0x02,0xe1] [all …]
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D | thumb2-mclass.s | 13 mrs r0, apsr 14 mrs r0, iapsr 15 mrs r0, eapsr 16 mrs r0, xpsr 17 mrs r0, ipsr 18 mrs r0, epsr 19 mrs r0, iepsr 20 mrs r0, msp 21 mrs r0, psp 22 mrs r0, primask [all …]
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D | thumbv7m.s | 13 mrs r0, basepri 14 mrs r0, basepri_max 15 mrs r0, faultmask 17 @ CHECK: mrs r0, basepri @ encoding: [0xef,0xf3,0x11,0x80] 18 @ CHECK: mrs r0, basepri_max @ encoding: [0xef,0xf3,0x12,0x80] 19 @ CHECK: mrs r0, faultmask @ encoding: [0xef,0xf3,0x13,0x80] 34 @ CHECK-V6M-NEXT: mrs r0, basepri 36 @ CHECK-V6M-NEXT: mrs r0, basepri_max 38 @ CHECK-V6M-NEXT: mrs r0, faultmask
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/external/llvm/test/MC/Disassembler/AArch64/ |
D | trace-regs.txt | 5 # CHECK: mrs x8, {{trcstatr|TRCSTATR}} 7 # CHECK: mrs x9, {{trcidr8|TRCIDR8}} 9 # CHECK: mrs x11, {{trcidr9|TRCIDR9}} 11 # CHECK: mrs x25, {{trcidr10|TRCIDR10}} 13 # CHECK: mrs x7, {{trcidr11|TRCIDR11}} 15 # CHECK: mrs x7, {{trcidr12|TRCIDR12}} 17 # CHECK: mrs x6, {{trcidr13|TRCIDR13}} 19 # CHECK: mrs x27, {{trcidr0|TRCIDR0}} 21 # CHECK: mrs x29, {{trcidr1|TRCIDR1}} 23 # CHECK: mrs x4, {{trcidr2|TRCIDR2}} [all …]
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D | gicv3-regs.txt | 5 # CHECK: mrs x8, {{icc_iar1_el1|ICC_IAR1_EL1}} 7 # CHECK: mrs x26, {{icc_iar0_el1|ICC_IAR0_EL1}} 9 # CHECK: mrs x2, {{icc_hppir1_el1|ICC_HPPIR1_EL1}} 11 # CHECK: mrs x17, {{icc_hppir0_el1|ICC_HPPIR0_EL1}} 13 # CHECK: mrs x29, {{icc_rpr_el1|ICC_RPR_EL1}} 15 # CHECK: mrs x4, {{ich_vtr_el2|ICH_VTR_EL2}} 17 # CHECK: mrs x24, {{ich_eisr_el2|ICH_EISR_EL2}} 19 # CHECK: mrs x9, {{ich_elsr_el2|ICH_ELSR_EL2}} 21 # CHECK: mrs x24, {{icc_bpr1_el1|ICC_BPR1_EL1}} 23 # CHECK: mrs x14, {{icc_bpr0_el1|ICC_BPR0_EL1}} [all …]
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D | basic-a64-instructions.txt | 3316 # CHECK: mrs x9, {{teecr32_el1|TEECR32_EL1}} 3317 # CHECK: mrs x9, {{osdtrrx_el1|OSDTRRX_EL1}} 3318 # CHECK: mrs x9, {{mdccsr_el0|MDCCSR_EL0}} 3319 # CHECK: mrs x9, {{mdccint_el1|MDCCINT_EL1}} 3320 # CHECK: mrs x9, {{mdscr_el1|MDSCR_EL1}} 3321 # CHECK: mrs x9, {{osdtrtx_el1|OSDTRTX_EL1}} 3322 # CHECK: mrs x9, {{dbgdtr_el0|DBGDTR_EL0}} 3323 # CHECK: mrs x9, {{dbgdtrrx_el0|DBGDTRRX_EL0}} 3324 # CHECK: mrs x9, {{oseccr_el1|OSECCR_EL1}} 3325 # CHECK: mrs x9, {{dbgvcr32_el2|DBGVCR32_EL2}} [all …]
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D | armv8.1a-pan.txt | 10 # CHECK: mrs x13, PAN
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/external/llvm/test/MC/Disassembler/ARM/ |
D | move-banked-regs-thumb.txt | 10 @ CHECK: mrs r2, r8_usr 11 @ CHECK: mrs r3, r9_usr 12 @ CHECK: mrs r5, r10_usr 13 @ CHECK: mrs r7, r11_usr 14 @ CHECK: mrs r11, r12_usr 15 @ CHECK: mrs r1, sp_usr 16 @ CHECK: mrs r2, lr_usr 26 @ CHECK: mrs r2, r8_fiq 27 @ CHECK: mrs r3, r9_fiq 28 @ CHECK: mrs r5, r10_fiq [all …]
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D | move-banked-regs-arm.txt | 11 @ CHECK: mrs r2, r8_usr 12 @ CHECK: mrs r3, r9_usr 13 @ CHECK: mrs r5, r10_usr 14 @ CHECK: mrs r7, r11_usr 15 @ CHECK: mrs r11, r12_usr 16 @ CHECK: mrs r1, sp_usr 17 @ CHECK: mrs r2, lr_usr 27 @ CHECK: mrs r2, r8_fiq 28 @ CHECK: mrs r3, r9_fiq 29 @ CHECK: mrs r5, r10_fiq [all …]
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D | thumb-MSR-MClass.txt | 7 # CHECK: mrs r0, apsr 8 # CHECK: mrs r0, iapsr 9 # CHECK: mrs r0, eapsr 10 # CHECK: mrs r0, xpsr 11 # CHECK: mrs r0, ipsr 12 # CHECK: mrs r0, epsr 13 # CHECK: mrs r0, iepsr 14 # CHECK: mrs r0, msp 15 # CHECK: mrs r0, psp 16 # CHECK: mrs r0, primask [all …]
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/external/llvm/test/CodeGen/AArch64/ |
D | arm64-tls-execs.ll | 12 ; CHECK: mrs x[[TP:[0-9]+]], TPIDR_EL0 27 ; CHECK: mrs [[TP:x[0-9]+]], TPIDR_EL0 41 ; CHECK: mrs x[[R1:[0-9]+]], TPIDR_EL0 55 ; CHECK: mrs x[[R1:[0-9]+]], TPIDR_EL0
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D | arm64-tls-dynamics.ll | 27 ; CHECK: mrs x[[TP:[0-9]+]], TPIDR_EL0 29 ; CHECK-NOLD: mrs x[[TP:[0-9]+]], TPIDR_EL0 55 ; CHECK: mrs [[TP:x[0-9]+]], TPIDR_EL0 85 ; CHECK: mrs x[[TPIDR:[0-9]+]], TPIDR_EL0 93 ; CHECK-NOLD: mrs x[[TPIDR:[0-9]+]], TPIDR_EL0 121 ; CHECK: mrs x[[TPIDR:[0-9]+]], TPIDR_EL0 129 ; CHECK-NOLD: mrs x[[TPIDR:[0-9]+]], TPIDR_EL0
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D | print-mrs-system-register.ll | 3 ; CHECK: mrs x0, CPM_IOACC_CTL_EL3 7 tail call void asm sideeffect "mrs x0, cpm_ioacc_ctl_el3", ""()
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/external/llvm/test/tools/llvm-objdump/AArch64/ |
D | macho-print-mrs.test | 1 RUN: llvm-objdump -d -m -no-show-raw-insn %p/Inputs/print-mrs.obj.macho-aarch64 | FileCheck %s 3 CHECK: 0: mrs x0, S3_7_C15_C2_0
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/external/lldb/tools/lldb-perf/lib/ |
D | MemoryGauge.h | 77 SetMaxResidentSize (mach_vm_size_t mrs) in SetMaxResidentSize() argument 79 m_max_resident_size = mrs; in SetMaxResidentSize()
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/external/llvm/test/CodeGen/ARM/ |
D | copy-cpsr.ll | 23 ; CHECK-ARM: mrs [[TMP:r[0-9]+]], apsr @ encoding: [0x00,0x{{[0-9a-f]}}0,0x0f,0xe1] 28 ; CHECK-THUMB: mrs [[TMP:r[0-9]+]], apsr @ encoding: [0xef,0xf3,0x00,0x8{{[0-9a-f]}}]
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