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Searched refs:orn (Results 1 – 25 of 46) sorted by relevance

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/external/llvm/test/CodeGen/Thumb2/
Dthumb2-orn.ll9 ; CHECK: orn r0, r0, r1
17 ; CHECK: orn r0, r0, r1
25 ; CHECK: orn r0, r0, r1
33 ; CHECK: orn r0, r0, r1
42 ; CHECK: orn r0, r0, r1, lsl #5
51 ; CHECK: orn r0, r0, r1, lsr #6
60 ; CHECK: orn r0, r0, r1, asr #7
71 ; CHECK: orn r0, r0, r0, ror #8
Dthumb2-orn2.ll10 ; CHECK: orn r0, r0, #187
19 ; CHECK: orn r0, r0, #11141290
28 ; CHECK: orn r0, r0, #-872363008
37 ; CHECK: orn r0, r0, #1114112
/external/llvm/test/MC/AArch64/
Darm64-logical-encoding.s204 orn w1, w2, w3
205 orn x1, x2, x3
206 orn w1, w2, w3, lsl #7
207 orn x1, x2, x3, lsl #7
208 orn w1, w2, w3, lsr #7
209 orn x1, x2, x3, lsr #7
210 orn w1, w2, w3, asr #7
211 orn x1, x2, x3, asr #7
212 orn w1, w2, w3, ror #7
213 orn x1, x2, x3, ror #7
[all …]
Dalias-logicalimm.s26 orn x0, x1, #2
31 orn w2, w1, #3
Dneon-bitwise-instructions.s45 orn v0.8b, v1.8b, v2.8b
46 orn v0.16b, v1.16b, v2.16b
Darm64-aliases.s156 orn w4, wzr, w9
164 orn w4, wzr, w9, lsl #1
Dbasic-a64-diagnostics.s2985 orn wsp, w3, w5
2987 orn x2, x6, sp, lsl #3
Dbasic-a64-instructions.s3306 orn x3, x5, x7, asr #0
3307 orn w2, w5, w29
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-logical.txt214 # CHECK: orn w1, w2, w3
215 # CHECK: orn x1, x2, x3
216 # CHECK: orn w1, w2, w3, lsl #7
217 # CHECK: orn x1, x2, x3, lsl #7
218 # CHECK: orn w1, w2, w3, lsr #7
219 # CHECK: orn x1, x2, x3, lsr #7
220 # CHECK: orn w1, w2, w3, asr #7
221 # CHECK: orn x1, x2, x3, asr #7
222 # CHECK: orn w1, w2, w3, ror #7
223 # CHECK: orn x1, x2, x3, ror #7
/external/llvm/test/CodeGen/AArch64/
Dlogical_shifted_reg.ll14 ; First check basic and/bic/or/orn/eor/eon patterns with no shift
28 ; CHECK: orn {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
53 ; CHECK: orn {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
78 ; CHECK: orn {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #1
104 ; First check basic and/bic/or/orn/eor/eon patterns with no shift
118 ; CHECK: orn {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
143 ; CHECK: orn {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
168 ; CHECK: orn {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #1
Dneon-bitwise-instructions.ll67 ; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
75 ; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
472 ; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
480 ; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
488 ; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
496 ; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
504 ; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
512 ; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dcr.ll99 declare i32 @llvm.hexagon.C4.and.orn(i32, i32, i32)
101 %z = call i32@llvm.hexagon.C4.and.orn(i32 %a, i32 %b, i32 %c)
120 declare i32 @llvm.hexagon.C2.orn(i32, i32)
122 %z = call i32@llvm.hexagon.C2.orn(i32 %a, i32 %b)
127 declare i32 @llvm.hexagon.C4.or.orn(i32, i32, i32)
129 %z = call i32@llvm.hexagon.C4.or.orn(i32 %a, i32 %b, i32 %c)
Dalu32_alu.ll55 declare i32 @llvm.hexagon.A4.orn(i32, i32)
57 %z = call i32 @llvm.hexagon.A4.orn(i32 %a, i32 %b)
/external/llvm/test/MC/Sparc/
Dsparc-alu-instructions.s31 ! CHECK: orn %g1, %g2, %g3 ! encoding: [0x86,0x30,0x40,0x02]
32 orn %g1, %g2, %g3
/external/valgrind/none/tests/arm64/
Dinteger.stdout.exp644 orn x7,x8,x9,lsl #0 :: rd dbcfa71ff9e7a9f5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00…
645 orn x7,x8,x9,lsl #1 :: rd fd7dfbefe776f78b rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00…
646 orn x7,x8,x9,lsl #62 :: rd ffffffffffffffff rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 0…
647 orn x7,x8,x9,lsl #63 :: rd ffffffffffffffff rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 0…
648 orn x7,x8,x9,lsr #0 :: rd dbcfa71ff9e7a9f5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00…
649 orn x7,x8,x9,lsr #1 :: rd ff7bfaffe5ddbcea rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00…
650 orn x7,x8,x9,lsr #62 :: rd ffffffffffffffff rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 0…
651 orn x7,x8,x9,lsr #63 :: rd ffffffffffffffff rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 0…
652 orn x7,x8,x9,asr #0 :: rd dbcfa71ff9e7a9f5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00…
653 orn x7,x8,x9,asr #1 :: rd ff7bfaffe5ddbcea rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00…
[all …]
/external/llvm/test/CodeGen/Generic/
D2003-07-08-BadCastToBool.ll10 ;; (2) (A or NOT(B)) was being folded into A orn B, which is ok
/external/v8/test/cctest/
Dtest-disasm-arm64.cc658 COMPARE(orn(w11, w12, Operand(0x40004000)), in TEST_()
660 COMPARE(orn(x13, x14, Operand(0x8181818181818181L)), in TEST_()
718 COMPARE(orn(w15, w16, Operand(w17)), "orn w15, w16, w17"); in TEST_()
719 COMPARE(orn(x18, x19, Operand(x20, LSL, 13)), "orn x18, x19, x20, lsl #13"); in TEST_()
720 COMPARE(orn(w21, w22, Operand(w23, LSR, 14)), "orn w21, w22, w23, lsr #14"); in TEST_()
721 COMPARE(orn(x24, x25, Operand(x26, ASR, 15)), "orn x24, x25, x26, asr #15"); in TEST_()
722 COMPARE(orn(w27, w28, Operand(w29, ROR, 16)), "orn w27, w28, w29, ror #16"); in TEST_()
753 COMPARE(orn(w0, wzr, Operand(w1)), "mvn w0, w1"); in TEST_()
754 COMPARE(orn(w2, wzr, Operand(w3, ASR, 5)), "mvn w2, w3, asr #5"); in TEST_()
755 COMPARE(orn(x0, xzr, Operand(x1)), "mvn x0, x1"); in TEST_()
[all …]
/external/llvm/test/MC/Disassembler/Sparc/
Dsparc.txt36 # CHECK: orn %g1, %g2, %g3
/external/llvm/test/MC/ARM/
Dbasic-thumb2-instructions.s1604 orn r4, r5, #0xf000
1605 orn r4, r5, r6
1607 orn r4, r5, r6, lsl #5
1609 orn r4, r5, r6, lsr #5
1611 orn r4, r5, r6, ror #5
1613 @ CHECK: orn r4, r5, #61440 @ encoding: [0x65,0xf4,0x70,0x44]
1614 @ CHECK: orn r4, r5, r6 @ encoding: [0x65,0xea,0x06,0x04]
1616 @ CHECK: orn r4, r5, r6, lsl #5 @ encoding: [0x65,0xea,0x46,0x14]
1618 @ CHECK: orn r4, r5, r6, lsr #5 @ encoding: [0x65,0xea,0x56,0x14]
1620 @ CHECK: orn r4, r5, r6, ror #5 @ encoding: [0x65,0xea,0x76,0x14]
/external/llvm/test/MC/Disassembler/ARM/
Dthumb2.txt1219 # CHECK: orn r4, r5, #61440
1220 # CHECK: orn r4, r5, r6
1222 # CHECK: orn r4, r5, r6, lsl #5
1224 # CHECK: orn r4, r5, r6, lsr #5
1226 # CHECK: orn r4, r5, r6, ror #5
/external/vixl/test/
Dtest-disasm-a64.cc757 COMPARE(orn(w11, w12, Operand(0x40004000)), in TEST()
759 COMPARE(orn(x13, x14, Operand(0x8181818181818181)), in TEST()
817 COMPARE(orn(w15, w16, Operand(w17)), "orn w15, w16, w17"); in TEST()
818 COMPARE(orn(x18, x19, Operand(x20, LSL, 13)), "orn x18, x19, x20, lsl #13"); in TEST()
819 COMPARE(orn(w21, w22, Operand(w23, LSR, 14)), "orn w21, w22, w23, lsr #14"); in TEST()
820 COMPARE(orn(x24, x25, Operand(x26, ASR, 15)), "orn x24, x25, x26, asr #15"); in TEST()
821 COMPARE(orn(w27, w28, Operand(w29, ROR, 16)), "orn w27, w28, w29, ror #16"); in TEST()
852 COMPARE(orn(w0, wzr, Operand(w1)), "mvn w0, w1"); in TEST()
853 COMPARE(orn(w2, wzr, Operand(w3, ASR, 5)), "mvn w2, w3, asr #5"); in TEST()
854 COMPARE(orn(x0, xzr, Operand(x1)), "mvn x0, x1"); in TEST()
[all …]
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.td477 "orn $rs1, $rs2, $rd",
481 "orn $rs1, $simm13, $rd", []>;
DSparcInstr64Bit.td155 "orn $b, $c, $dst",
/external/v8/src/arm64/
Dassembler-arm64.cc1219 void Assembler::orn(const Register& rd, in orn() function in v8::internal::Assembler
1739 orn(rd, AppropriateZeroRegFor(rd), operand); in mvn()
/external/vixl/doc/
Dsupported-instructions.md900 void orn(const Register& rd, const Register& rn, const Operand& operand)
2762 Bitwise orn.
2764 void orn(const VRegister& vd,

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