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/external/llvm/test/MC/AArch64/
Dneon-mov.s102 orr v0.2s, #1
103 orr v1.2s, #0
104 orr v0.2s, #1, lsl #8
105 orr v0.2s, #1, lsl #16
106 orr v0.2s, #1, lsl #24
107 orr v0.4s, #1
108 orr v0.4s, #1, lsl #8
109 orr v0.4s, #1, lsl #16
110 orr v0.4s, #1, lsl #24
111 orr v31.4h, #1
[all …]
Darm64-logical-encoding.s34 orr w1, w2, #0x4000
35 orr x1, x2, #0x8000
37 ; CHECK: orr w1, w2, #0x4000 ; encoding: [0x41,0x00,0x12,0x32]
38 ; CHECK: orr x1, x2, #0x8000 ; encoding: [0x41,0x00,0x71,0xb2]
40 orr w8, wzr, #0x1
41 orr x8, xzr, #0x1
43 ; CHECK: orr w8, wzr, #0x1 ; encoding: [0xe8,0x03,0x00,0x32]
44 ; CHECK: orr x8, xzr, #0x1 ; encoding: [0xe8,0x03,0x40,0xb2]
182 orr w1, w2, w3
183 orr x1, x2, x3
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-movi.ll10 ; CHECK: orr x0, xzr, #0x700000007
17 ; CHECK: orr x0, xzr, #0xc0000003c0000003
24 ; CHECK: orr x0, xzr, #0xeeeeeeeeeeeeeeee
31 ; CHECK: orr w0, wzr, #0xff0000
38 ; CHECK: orr w0, wzr, #0xaaaaaaaa
99 ; CHECK: orr x0, xzr, #0xffff0000ffff0
106 ; CHECK: orr x0, xzr, #0xffff0000ffff0
113 ; CHECK: orr x0, xzr, #0xffff0000ffff0
120 ; CHECK: orr x0, xzr, #0xffff0000ffff0
128 ; CHECK: orr x0, xzr, #0xff00ff00ff00ff00
[all …]
Dmovw-consts.ll12 ; CHECK: orr w0, wzr, #0x1
18 ; CHECK: orr w0, wzr, #0xffff
24 ; CHECK: orr w0, wzr, #0x10000
30 ; CHECK: orr w0, wzr, #0xffff0000
36 ; CHECK: orr x0, xzr, #0x100000000
42 ; CHECK: orr x0, xzr, #0xffff00000000
48 ; CHECK: orr x0, xzr, #0x1000000000000
85 ; CHECK: orr {{w[0-9]+}}, wzr, #0x1
92 ; CHECK: orr {{w[0-9]+}}, wzr, #0xffff
99 ; CHECK: orr {{w[0-9]+}}, wzr, #0x10000
[all …]
Darm64-patchpoint-webkit_jscc.ll37 ; CHECK: orr w[[REG:[0-9]+]], wzr, #0x6
39 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x4
41 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x2
50 ; FAST: orr [[REG1:x[0-9]+]], xzr, #0x2
51 ; FAST-NEXT: orr [[REG2:w[0-9]+]], wzr, #0x4
52 ; FAST-NEXT: orr [[REG3:x[0-9]+]], xzr, #0x6
73 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x8
75 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x6
77 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x4
79 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x2
[all …]
Dlogical-imm.ll33 ; CHECK: orr {{w[0-9]+}}, {{w[0-9]+}}, #0xaaaaaaaa
37 ; CHECK: orr {{w[0-9]+}}, {{w[0-9]+}}, #0xfff0fff0
41 ; CHECK: orr {{x[0-9]+}}, {{x[0-9]+}}, #0x8181818181818181
45 ; CHECK: orr {{x[0-9]+}}, {{x[0-9]+}}, #0xffc3ffc3ffc3ffc3
76 ; CHECK: orr {{w[0-9]+}}, wzr, #0xaaaaaaaa
80 ; CHECK: orr {{x[0-9]+}}, xzr, #0x9999999999999999
Darm64-long-shift.ll6 ; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
9 ; CHECK-NEXT: orr [[XREG_6:x[0-9]+]], [[XREG_3]], [[XREG_0]]
25 ; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
28 ; CHECK-NEXT: orr [[XREG_4:x[0-9]+]], [[XREG_0]], [[XREG_3]]
45 ; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
48 ; CHECK-NEXT: orr [[XREG_4:x[0-9]+]], [[XREG_0]], [[XREG_3]]
Dfast-isel-logic-op.ll130 ; CHECK: orr [[REG:w[0-9]+]], w0, w1
137 ; CHECK: orr [[REG:w[0-9]+]], w0, w1
145 ; CHECK: orr [[REG:w[0-9]+]], w0, w1
153 ; CHECK: orr w0, w0, w1
160 ; CHECK: orr x0, x0, x1
167 ; CHECK: orr [[REG:w[0-9]+]], w0, #0xf
175 ; CHECK: orr [[REG:w[0-9]+]], w0, #0xff
183 ; CHECK: orr w0, w0, #0xff
190 ; CHECK: orr x0, x0, #0xff
197 ; CHECK: orr [[REG:w[0-9]+]], w0, w1, lsl #4
[all …]
Dneon-bitwise-instructions.ll20 ; CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
27 ; CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
99 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}
106 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8
113 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16
120 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #24
127 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}
134 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8
141 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16
148 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #24
[all …]
Dmachine_cse_impdef_killflags.ll9 ; CHECK-DAG: orr [[REG1:w[0-9]+]], wzr, #0x1
10 ; CHECK-DAG: orr [[REG2:x[0-9]+]], xzr, #0x2
11 ; CHECK-DAG: orr [[REG3:x[0-9]+]], xzr, #0x3
Darm64-unaligned_ldst.ll7 ; CHECK-NOT: orr
20 ; CHECK-NOT: orr
33 ; CHECK-NOT: orr
Dor-combine.ll7 ; CHECK-NOT: orr
18 ; CHECK: orr [[FULL_MASK:w[0-9]+]], w1, w2
33 ; CHECK-DAG: orr w0, w1, w2
/external/libvpx/libvpx/vp8/common/arm/armv6/
Dloopfilter_v6.asm32 orr $b1, $b0, $b1, lsl #8 ; 12 02 10 00
33 orr $b3, $b2, $b3, lsl #8 ; 32 22 30 20
39 orr $a0, $a0, $a1, lsl #8 ; 13 03 11 01
40 orr $a2, $a2, $a3, lsl #8 ; 33 23 31 21
76 orr r4, r4, r4, lsl #8
78 orr r2, r2, r2, lsl #8
80 orr r4, r4, r4, lsl #16
81 orr r3, r3, r3, lsl #8
82 orr r2, r2, r2, lsl #16
83 orr r3, r3, r3, lsl #16
[all …]
Ddc_only_idct_add_v6.asm31 orr r0, r0, r0, lsl #16 ; a1 | a1
43 orr r5, r5, r4, lsl #8
44 orr r7, r7, r6, lsl #8
58 orr r5, r5, r4, lsl #8
59 orr r7, r7, r6, lsl #8
Dsimpleloopfilter_v6.asm30 orr $b1, $b0, $b1, lsl #8 ; 12 02 10 00
31 orr $b3, $b2, $b3, lsl #8 ; 32 22 30 20
37 orr $a0, $a0, $a1, lsl #8 ; 13 03 11 01
38 orr $a2, $a2, $a3, lsl #8 ; 33 23 31 21
66 orr r12, r12, r12, lsl #8 ; blimit
68 orr r12, r12, r12, lsl #16 ; blimit
183 orr r7, r7, r8 ; abs(p1 - q1)
184 orr r9, r9, r10 ; abs(p0 - q0)
/external/boringssl/linux-arm/crypto/aes/
Daes-armv4.S184 orr r0,r0,r4,lsl#8
186 orr r0,r0,r5,lsl#16
188 orr r0,r0,r6,lsl#24
191 orr r1,r1,r4,lsl#8
193 orr r1,r1,r5,lsl#16
195 orr r1,r1,r6,lsl#24
198 orr r2,r2,r4,lsl#8
200 orr r2,r2,r5,lsl#16
202 orr r2,r2,r6,lsl#24
205 orr r3,r3,r4,lsl#8
[all …]
/external/llvm/test/CodeGen/Thumb2/
Dthumb2-orr2.ll9 ; CHECK: orr r0, r0, #187
17 ; CHECK: orr r0, r0, #11141290
25 ; CHECK: orr r0, r0, #-872363008
33 ; CHECK: orr r0, r0, #1145324612
41 ; CHECK: orr r0, r0, #1114112
Dthumb2-orr.ll12 ; CHECK: orr.w r0, r0, r1, lsl #5
20 ; CHECK: orr.w r0, r0, r1, lsr #6
28 ; CHECK: orr.w r0, r0, r1, asr #7
36 ; CHECK: orr.w r0, r0, r0, ror #8
/external/boringssl/linux-aarch64/crypto/sha/
Dsha1-armv8.S47 orr w25,w25,w26
61 orr w25,w25,w26
72 orr w25,w25,w26
86 orr w25,w25,w26
97 orr w25,w25,w26
111 orr w25,w25,w26
122 orr w25,w25,w26
136 orr w25,w25,w26
147 orr w25,w25,w26
161 orr w25,w25,w26
[all …]
Dsha256-armv8.S48 orr w17,w17,w19 // Ch(e,f,g)
73 orr w17,w17,w28 // Ch(e,f,g)
97 orr w17,w17,w19 // Ch(e,f,g)
122 orr w17,w17,w28 // Ch(e,f,g)
146 orr w17,w17,w19 // Ch(e,f,g)
171 orr w17,w17,w28 // Ch(e,f,g)
195 orr w17,w17,w19 // Ch(e,f,g)
220 orr w17,w17,w28 // Ch(e,f,g)
244 orr w17,w17,w19 // Ch(e,f,g)
269 orr w17,w17,w28 // Ch(e,f,g)
[all …]
Dsha512-armv8.S42 orr x17,x17,x19 // Ch(e,f,g)
67 orr x17,x17,x28 // Ch(e,f,g)
91 orr x17,x17,x19 // Ch(e,f,g)
116 orr x17,x17,x28 // Ch(e,f,g)
140 orr x17,x17,x19 // Ch(e,f,g)
165 orr x17,x17,x28 // Ch(e,f,g)
189 orr x17,x17,x19 // Ch(e,f,g)
214 orr x17,x17,x28 // Ch(e,f,g)
238 orr x17,x17,x19 // Ch(e,f,g)
263 orr x17,x17,x28 // Ch(e,f,g)
[all …]
/external/llvm/test/MC/ARM/
Darm-arithmetic-aliases.s36 orr r2, r2, #6 label
37 orr r2, #6 label
38 orr r2, r2, r3 label
39 orr r2, r3 label
41 @ CHECK: orr r2, r2, #6 @ encoding: [0x06,0x20,0x82,0xe3]
42 @ CHECK: orr r2, r2, #6 @ encoding: [0x06,0x20,0x82,0xe3]
43 @ CHECK: orr r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe1]
44 @ CHECK: orr r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe1]
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-logical.txt41 # CHECK: orr w1, w2, #0x4000
42 # CHECK: orr x1, x2, #0x8000
43 # CHECK: orr sp, x2, #0x8000
192 # CHECK: orr w1, w2, w3
193 # CHECK: orr x1, x2, x3
194 # CHECK: orr w1, w2, w3, lsl #6
195 # CHECK: orr x1, x2, x3, lsl #6
196 # CHECK: orr w1, w2, w3, lsr #6
197 # CHECK: orr x1, x2, x3, lsr #6
198 # CHECK: orr w1, w2, w3, asr #6
[all …]
/external/compiler-rt/lib/builtins/arm/
Dsync_fetch_and_or_8.S19 orr rD_LO, rN_LO, rM_LO ; \
20 orr rD_HI, rN_HI, rM_HI
/external/llvm/test/CodeGen/ARM/
Dlong_shift.ll34 ; CHECK-LE-NEXT: orr r0, r0, r1, lsl r3
40 ; CHECK-BE-NEXT: orr r1, r1, r0, lsl r2
55 ; CHECK-LE-NEXT: orr r0, r0, r1, lsl r3
61 ; CHECK-BE-NEXT: orr r1, r1, r0, lsl r2

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