| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstr64Bit.td | 239 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
240 "ldarx $rD, $ptr", IIC_LdStLDARX, []>;
244 def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
245 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isDOT;
394 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
395 "li $rD, $imm", IIC_IntSimple,
396 [(set i64:$rD, imm64SExt16:$imm)]>;
397 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
398 "lis $rD, $imm", IIC_IntSimple,
399 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
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| D | PPCInstrInfo.td | 1008 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
1009 "UPDATE_VRSAVE $rD, $rS", []>;
1477 def LBARX : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src),
1478 "lbarx $rD, $src", IIC_LdStLWARX, []>,
1481 def LHARX : XForm_1<31, 116, (outs gprc:$rD), (ins memrr:$src),
1482 "lharx $rD, $src", IIC_LdStLWARX, []>,
1485 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1486 "lwarx $rD, $src", IIC_LdStLWARX, []>;
1490 def LBARXL : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src),
1491 "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
[all …]
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| /external/lzma/Asm/x86/ |
| D | 7zCrcOpt.asm | 8 rD equ r2 define
21 SRCDAT equ rN + rD + 4 *
36 movzx x6, BYTE PTR [rD]
37 inc rD
54 test rD, 7
61 add rN, rD
65 sub rD, rN
71 mov rD, rN
73 sub rN, rD
110 add rD, 8
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| /external/aac/libFDK/src/ |
| D | FDK_crc.cpp | 410 CCrcRegData *rD = &hCrcInfo->crcRegData[reg]; in crcCalc() local
415 FDKpushBiDirectional(&bsReader, -(INT)(rD->validBits-FDKgetValidBits(&bsReader))); in crcCalc()
419 FDKpushBiDirectional(&bsReader, rD->validBits); in crcCalc()
423 rBits = (rD->maxBits>=0) ? rD->maxBits : -rD->maxBits; /* ramaining bits */ in crcCalc()
424 if ((rD->maxBits>0) && (((INT)rD->bitBufCntBits>>3<<3)<rBits) ) { in crcCalc()
425 bits = rD->bitBufCntBits; in crcCalc()
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| /external/valgrind/VEX/priv/ |
| D | guest_arm_toIR.c | 7831 void mk_neon_elem_load_to_one_lane( UInt rD, UInt inc, UInt index, in mk_neon_elem_load_to_one_lane() argument
7837 putDRegI64(rD, triop(Iop_SetElem8x8, getDRegI64(rD), mkU8(index), in mk_neon_elem_load_to_one_lane()
7841 putDRegI64(rD, triop(Iop_SetElem16x4, getDRegI64(rD), mkU8(index), in mk_neon_elem_load_to_one_lane()
7845 putDRegI64(rD, triop(Iop_SetElem32x2, getDRegI64(rD), mkU8(index), in mk_neon_elem_load_to_one_lane()
7854 putDRegI64(rD + i * inc, in mk_neon_elem_load_to_one_lane()
7856 getDRegI64(rD + i * inc), in mk_neon_elem_load_to_one_lane()
7864 putDRegI64(rD + i * inc, in mk_neon_elem_load_to_one_lane()
7866 getDRegI64(rD + i * inc), in mk_neon_elem_load_to_one_lane()
7874 putDRegI64(rD + i * inc, in mk_neon_elem_load_to_one_lane()
7876 getDRegI64(rD + i * inc), in mk_neon_elem_load_to_one_lane()
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| D | host_arm64_defs.c | 888 ARM64Instr* ARM64Instr_LdSt64 ( Bool isLoad, HReg rD, ARM64AMode* amode ) { in ARM64Instr_LdSt64() argument
892 i->ARM64in.LdSt64.rD = rD; in ARM64Instr_LdSt64()
896 ARM64Instr* ARM64Instr_LdSt32 ( Bool isLoad, HReg rD, ARM64AMode* amode ) { in ARM64Instr_LdSt32() argument
900 i->ARM64in.LdSt32.rD = rD; in ARM64Instr_LdSt32()
904 ARM64Instr* ARM64Instr_LdSt16 ( Bool isLoad, HReg rD, ARM64AMode* amode ) { in ARM64Instr_LdSt16() argument
908 i->ARM64in.LdSt16.rD = rD; in ARM64Instr_LdSt16()
912 ARM64Instr* ARM64Instr_LdSt8 ( Bool isLoad, HReg rD, ARM64AMode* amode ) { in ARM64Instr_LdSt8() argument
916 i->ARM64in.LdSt8.rD = rD; in ARM64Instr_LdSt8()
1051 ARM64Instr* ARM64Instr_VCvtI2F ( ARM64CvtOp how, HReg rD, HReg rS ) { in ARM64Instr_VCvtI2F() argument
1055 i->ARM64in.VCvtI2F.rD = rD; in ARM64Instr_VCvtI2F()
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| D | host_arm_defs.c | 1137 Bool isLoad, HReg rD, ARMAMode1* amode ) { in ARMInstr_LdSt32() argument
1142 i->ARMin.LdSt32.rD = rD; in ARMInstr_LdSt32()
1149 HReg rD, ARMAMode2* amode ) { in ARMInstr_LdSt16() argument
1155 i->ARMin.LdSt16.rD = rD; in ARMInstr_LdSt16()
1161 Bool isLoad, HReg rD, ARMAMode1* amode ) { in ARMInstr_LdSt8U() argument
1166 i->ARMin.LdSt8U.rD = rD; in ARMInstr_LdSt8U()
1171 ARMInstr* ARMInstr_Ld8S ( ARMCondCode cc, HReg rD, ARMAMode2* amode ) { in ARMInstr_Ld8S() argument
1175 i->ARMin.Ld8S.rD = rD; in ARMInstr_Ld8S()
1504 ARMInstr* ARMInstr_Add32 ( HReg rD, HReg rN, UInt imm32 ) { in ARMInstr_Add32() argument
1511 i->ARMin.Alu.dst = rD; in ARMInstr_Add32()
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| D | host_arm64_defs.h | 582 HReg rD; member
588 HReg rD; member
594 HReg rD; member
600 HReg rD; member
707 HReg rD; // dst, a D or S register member
713 HReg rD; // dst, a W or X register member
841 HReg rD; member
919 extern ARM64Instr* ARM64Instr_VCvtI2F ( ARM64CvtOp how, HReg rD, HReg rS );
920 extern ARM64Instr* ARM64Instr_VCvtF2I ( ARM64CvtOp how, HReg rD, HReg rS,
945 extern ARM64Instr* ARM64Instr_VDfromX ( HReg rD, HReg rX );
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| D | host_arm_defs.h | 671 HReg rD; member
679 HReg rD; member
686 HReg rD; member
692 HReg rD; member
943 HReg rD; member
1017 extern ARMInstr* ARMInstr_Add32 ( HReg rD, HReg rN, UInt imm32 );
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| D | host_arm64_isel.c | 3035 HReg rD = newVRegD(env); in iselDblExpr_wrk() local
3037 addInstr(env, ARM64Instr_VLdStD(True/*isLoad*/, rD, rN, offs)); in iselDblExpr_wrk()
3038 return rD; in iselDblExpr_wrk()
3222 HReg rD = newVRegD(env); in iselFltExpr_wrk() local
3224 addInstr(env, ARM64Instr_VLdStS(True/*isLoad*/, rD, rN, offs)); in iselFltExpr_wrk()
3225 return rD; in iselFltExpr_wrk()
3369 HReg rD = newVRegD(env); in iselF16Expr_wrk() local
3371 addInstr(env, ARM64Instr_VLdStH(True/*isLoad*/, rD, rN, offs)); in iselF16Expr_wrk()
3372 return rD; in iselF16Expr_wrk()
3535 HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data); in iselStmt() local
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| D | host_arm_isel.c | 2328 HReg rD = newVRegD(env); in iselNeon64Expr_wrk() local
2344 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, False)); in iselNeon64Expr_wrk()
2345 addInstr(env, ARMInstr_NDual(ARMneon_TRN, rD, rM, size, False)); in iselNeon64Expr_wrk()
2346 return resRd ? rD : rM; in iselNeon64Expr_wrk()
2354 HReg rD = newVRegD(env); in iselNeon64Expr_wrk() local
2368 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, False)); in iselNeon64Expr_wrk()
2369 addInstr(env, ARMInstr_NDual(ARMneon_ZIP, rD, rM, size, False)); in iselNeon64Expr_wrk()
2370 return resRd ? rD : rM; in iselNeon64Expr_wrk()
2378 HReg rD = newVRegD(env); in iselNeon64Expr_wrk() local
2392 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, False)); in iselNeon64Expr_wrk()
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| D | guest_ppc_toIR.c | 3380 IRTemp rD = newTemp(ty); in dis_int_arith() local
3391 assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA), in dis_int_arith()
3394 mkexpr(rD), mkexpr(rA), mkSzExtendS16(ty, uimm16), in dis_int_arith()
3400 assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA), in dis_int_arith()
3403 mkexpr(rD), mkexpr(rA), mkSzExtendS16(ty, uimm16), in dis_int_arith()
3414 assign( rD, mkSzExtendS16(ty, uimm16) ); in dis_int_arith()
3417 assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA), in dis_int_arith()
3426 assign( rD, mkSzExtendS32(ty, uimm16 << 16) ); in dis_int_arith()
3429 assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA), in dis_int_arith()
3437 assign( rD, unop(Iop_128to64, in dis_int_arith()
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| D | guest_amd64_toIR.c | 22164 UInt rD = gregOfRexRM(pfx, modrm); in dis_VEX_NDS_128_AnySimdPfx_0F_WIG() local
22181 name, nameXMMReg(rSR), nameXMMReg(rSL), nameXMMReg(rD)); in dis_VEX_NDS_128_AnySimdPfx_0F_WIG()
22187 name, dis_buf, nameXMMReg(rSL), nameXMMReg(rD)); in dis_VEX_NDS_128_AnySimdPfx_0F_WIG()
22210 putYMMRegLoAndZU(rD, mkexpr(res)); in dis_VEX_NDS_128_AnySimdPfx_0F_WIG()
22518 UInt rD = getVexNvvvv(pfx); in dis_AVX128_shiftE_to_V_imm() local
22528 nameXMMReg(rD)); in dis_AVX128_shiftE_to_V_imm()
22560 putYMMRegLoAndZU( rD, mkexpr(e1) ); in dis_AVX128_shiftE_to_V_imm()
22575 UInt rD = getVexNvvvv(pfx); in dis_AVX256_shiftE_to_V_imm() local
22585 nameYMMReg(rD)); in dis_AVX256_shiftE_to_V_imm()
22618 putYMMReg( rD, mkexpr(e1) ); in dis_AVX256_shiftE_to_V_imm()
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| D | guest_arm64_toIR.c | 2464 UInt rD = INSN(4,0); in dis_ARM64_data_processing_immediate() local
2473 putIReg64orZR(rD, mkU64(val)); in dis_ARM64_data_processing_immediate()
2474 DIP("adr%s %s, 0x%llx\n", bP ? "p" : "", nameIReg64orZR(rD), val); in dis_ARM64_data_processing_immediate()
2815 UInt rD = INSN(4,0); in dis_ARM64_data_processing_register() local
2828 if (rD != 31) putIRegOrZR(is64, rD, mkexpr(res)); in dis_ARM64_data_processing_register()
2834 nameIRegOrZR(is64, rD), nameIRegOrZR(is64, rN), in dis_ARM64_data_processing_register()
2857 UInt rD = INSN(4,0); in dis_ARM64_data_processing_register() local
2889 if (rD != 31) putIRegOrZR(is64, rD, mkexpr(res)); in dis_ARM64_data_processing_register()
2897 nameIRegOrZR(is64, rD), nameIRegOrZR(is64, rN), in dis_ARM64_data_processing_register()
2923 UInt rD = INSN(4,0); in dis_ARM64_data_processing_register() local
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| /external/compiler-rt/lib/builtins/arm/ |
| D | sync-ops.h | 51 #define MINMAX_4(rD, rN, rM, cmp_kind) \ argument
53 mov rD, rM ; \
55 mov##cmp_kind rD, rN
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| D | sync_fetch_and_sub_4.S | 18 #define sub_4(rD, rN, rM) sub rD, rN, rM argument
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| D | sync_fetch_and_nand_4.S | 17 #define nand_4(rD, rN, rM) bic rD, rN, rM argument
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| D | sync_fetch_and_add_4.S | 18 #define add_4(rD, rN, rM) add rD, rN, rM argument
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| D | sync_fetch_and_and_4.S | 17 #define and_4(rD, rN, rM) and rD, rN, rM argument
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| D | sync_fetch_and_xor_4.S | 17 #define xor_4(rD, rN, rM) eor rD, rN, rM argument
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| D | sync_fetch_and_or_4.S | 17 #define or_4(rD, rN, rM) orr rD, rN, rM argument
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| D | sync_fetch_and_umax_4.S | 17 #define umax_4(rD, rN, rM) MINMAX_4(rD, rN, rM, hi) argument
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| D | sync_fetch_and_min_4.S | 17 #define min_4(rD, rN, rM) MINMAX_4(rD, rN, rM, lt) argument
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| D | sync_fetch_and_max_4.S | 17 #define max_4(rD, rN, rM) MINMAX_4(rD, rN, rM, gt) argument
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| D | sync_fetch_and_umin_4.S | 17 #define umin_4(rD, rN, rM) MINMAX_4(rD, rN, rM, lo) argument
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