| /external/libhevc/common/arm64/ |
| D | ihevc_itrans_recon_8x8.s | 187 smull v20.4s, v2.4h, v0.h[0] //// y0 * cos4(part of c0 and c1)
189 smull v18.4s, v3.4h, v1.h[2] //// y2 * sin2 (q3 is freed by this time)(part of d1)
192 smull v24.4s, v6.4h, v0.h[1] //// y1 * cos1(part of b0)
194 smull v26.4s, v6.4h, v0.h[3] //// y1 * cos3(part of b1)
196 smull v28.4s, v6.4h, v1.h[1] //// y1 * sin3(part of b2)
198 smull v30.4s, v6.4h, v1.h[3] //// y1 * sin1(part of b3)
208 smull v22.4s, v10.4h, v0.h[0] //// y4 * cos4(part of c0 and c1)
210 smull v6.4s, v3.4h, v0.h[2] //// y2 * cos2(part of d0)
304 smull v24.4s, v6.4h, v0.h[1] //// y1 * cos1(part of b0)
305 smull v26.4s, v6.4h, v0.h[3] //// y1 * cos3(part of b1)
[all …]
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| D | ihevc_inter_pred_chroma_vert_w16inp_w16out.s | 144 smull v0.4s, v0.4h, v16.4h //vmull_s16(src_tmp1, coeff_0)
147 smull v7.4s, v2.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
191 smull v30.4s, v0.4h, v16.4h //vmull_s16(src_tmp1, coeff_0)
199 smull v28.4s, v1.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
212 smull v26.4s, v2.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
222 smull v24.4s, v3.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
238 smull v30.4s, v0.4h, v16.4h //vmull_s16(src_tmp1, coeff_0)
248 smull v28.4s, v1.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
261 smull v26.4s, v2.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
273 smull v24.4s, v3.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
[all …]
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| D | ihevc_inter_pred_chroma_vert_w16inp.s | 144 smull v0.4s, v0.4h, v16.4h //vmull_s16(src_tmp1, coeff_0)
147 smull v7.4s, v2.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
192 smull v30.4s, v0.4h, v16.4h //vmull_s16(src_tmp1, coeff_0)
200 smull v28.4s, v1.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
213 smull v26.4s, v2.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
224 smull v24.4s, v3.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
241 smull v30.4s, v0.4h, v16.4h //vmull_s16(src_tmp1, coeff_0)
252 smull v28.4s, v1.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
266 smull v26.4s, v2.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
279 smull v24.4s, v3.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
[all …]
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| D | ihevc_itrans_recon_4x4_ttype1.s | 140 smull v6.4s, v1.4h, v4.h[2] //74 * pi2_src[1]
145 smull v5.4s, v1.4h, v4.h[2] //74 * pi2_src[1]
150 smull v7.4s, v0.4h, v4.h[2] // 74 * pi2_src[0]
154 smull v20.4s, v2.4h, v4.h[1] // 55 * pi2_src[2]
183 smull v6.4s, v22.4h, v4.h[2] //74 * pi2_src[1]
188 smull v5.4s, v22.4h, v4.h[2] //74 * pi2_src[1]
193 smull v7.4s, v21.4h, v4.h[2] // 74 * pi2_src[0]
198 smull v20.4s, v16.4h, v4.h[1] // 55 * pi2_src[2]
|
| D | ihevc_weighted_pred_bi.s | 222 smull v4.4s, v0.4h, v7.h[0] //vmull_n_s16(pi2_src1_val1, (int16_t) wgt0)
224 smull v5.4s, v1.4h, v7.h[1] //vmull_n_s16(pi2_src2_val1, (int16_t) wgt1)
229 … smull v6.4s, v2.4h, v7.h[0] //vmull_n_s16(pi2_src1_val2, (int16_t) wgt0) ii iteration
233 … smull v19.4s, v0.4h, v7.h[0] //vmull_n_s16(pi2_src1_val1, (int16_t) wgt0) iii iteration
236 … smull v17.4s, v3.4h, v7.h[1] //vmull_n_s16(pi2_src2_val2, (int16_t) wgt1) ii iteration
243 … smull v16.4s, v1.4h, v7.h[1] //vmull_n_s16(pi2_src2_val1, (int16_t) wgt1) iii iteration
251 … smull v18.4s, v2.4h, v7.h[0] //vmull_n_s16(pi2_src1_val2, (int16_t) wgt0) iv iteration
257 … smull v20.4s, v3.4h, v7.h[1] //vmull_n_s16(pi2_src2_val2, (int16_t) wgt1) iv iteration
|
| D | ihevc_inter_pred_filters_luma_vert_w16inp.s | 155 smull v19.4s, v1.4h, v23.4h //mul_res1 = vmull_u8(src_tmp2, coeffabs_1)//
171 smull v20.4s, v2.4h, v23.4h //mul_res2 = vmull_u8(src_tmp3, coeffabs_1)//
188 smull v21.4s, v3.4h, v23.4h
202 smull v30.4s, v4.4h, v23.4h
229 smull v19.4s, v1.4h, v23.4h //mul_res1 = vmull_u8(src_tmp2, coeffabs_1)//
246 smull v20.4s, v2.4h, v23.4h //mul_res2 = vmull_u8(src_tmp3, coeffabs_1)//
262 smull v21.4s, v3.4h, v23.4h
289 smull v30.4s, v4.4h, v23.4h
316 smull v19.4s, v1.4h, v23.4h //mul_res1 = vmull_u8(src_tmp2, coeffabs_1)//
330 smull v20.4s, v2.4h, v23.4h //mul_res2 = vmull_u8(src_tmp3, coeffabs_1)//
[all …]
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| D | ihevc_inter_pred_luma_vert_w16inp_w16out.s | 166 smull v19.4s,v1.4h,v23.4h //mul_res1 = smull_u8(src_tmp2, coeffabs_1)//
182 smull v20.4s,v2.4h,v23.4h //mul_res2 = smull_u8(src_tmp3, coeffabs_1)//
199 smull v21.4s,v3.4h,v23.4h
214 smull v31.4s,v4.4h,v23.4h
243 smull v19.4s,v1.4h,v23.4h //mul_res1 = smull_u8(src_tmp2, coeffabs_1)//
261 smull v20.4s,v2.4h,v23.4h //mul_res2 = smull_u8(src_tmp3, coeffabs_1)//
278 smull v21.4s,v3.4h,v23.4h
306 smull v31.4s,v4.4h,v23.4h
334 smull v19.4s,v1.4h,v23.4h //mul_res1 = smull_u8(src_tmp2, coeffabs_1)//
349 smull v20.4s,v2.4h,v23.4h //mul_res2 = smull_u8(src_tmp3, coeffabs_1)//
[all …]
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| D | ihevc_itrans_recon_16x16.s | 255 smull v24.4s, v6.4h, v0.h[1] //// y1 * cos1(part of b0)
256 smull v26.4s, v6.4h, v0.h[3] //// y1 * cos3(part of b1)
257 smull v28.4s, v6.4h, v1.h[1] //// y1 * sin3(part of b2)
258 smull v30.4s, v6.4h, v1.h[3] //// y1 * sin1(part of b3)
270 smull v12.4s, v10.4h, v0.h[0]
272 smull v14.4s, v10.4h, v0.h[0]
274 smull v16.4s, v10.4h, v0.h[0]
276 smull v18.4s, v10.4h, v0.h[0]
433 smull v24.4s, v6.4h, v2.h[1] //// y1 * cos1(part of b0)
434 smull v26.4s, v6.4h, v2.h[3] //// y1 * cos3(part of b1)
[all …]
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| D | ihevc_weighted_pred_uni.s | 175 smull v4.4s, v1.4h, v0.h[0] //vmull_n_s16(pi2_src_val1, (int16_t) wgt0)
180 smull v6.4s, v2.4h, v0.h[0] //vmull_n_s16(pi2_src_val2, (int16_t) wgt0) ii iteration
187 … smull v7.4s, v3.4h, v0.h[0] //vmull_n_s16(pi2_src_val1, (int16_t) wgt0) iii iteration
196 smull v16.4s, v5.4h, v0.h[0] //vmull_n_s16(pi2_src_val2, (int16_t) wgt0) iv iteration
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| D | ihevc_itrans_recon_4x4.s | 143 smull v6.4s, v1.4h, v4.h[1] //83 * pi2_src[1]
145 smull v5.4s, v1.4h, v4.h[3] //36 * pi2_src[1]
176 smull v6.4s, v1.4h, v4.h[1] //83 * pi2_src[1]
179 smull v5.4s, v1.4h, v4.h[3] //36 * pi2_src[1]
|
| D | ihevc_itrans_recon_32x32.s | 216 smull v24.4s, v8.4h, v0.h[1] //// y1 * cos1(part of b0)
217 smull v26.4s, v8.4h, v0.h[3] //// y1 * cos3(part of b1)
218 smull v28.4s, v8.4h, v1.h[1] //// y1 * sin3(part of b2)
219 smull v30.4s, v8.4h, v1.h[3] //// y1 * sin1(part of b3)
230 smull v20.4s, v10.4h, v0.h[0]
234 smull v22.4s, v10.4h, v0.h[0]
237 smull v16.4s, v10.4h, v0.h[0]
240 smull v18.4s, v10.4h, v0.h[0]
577 smull v24.4s, v8.4h, v2.h[1] //// y1 * cos1(part of b0)
578 smull v26.4s, v8.4h, v2.h[3] //// y1 * cos3(part of b1)
[all …]
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| /external/libmpeg2/common/armv8/ |
| D | impeg2_idct.s | 387 smull v20.4s, v2.4h, v0.4h[0] //// y0 * cos4(part of c0 and c1)
389 smull v18.4s, v3.4h, v1.4h[2] //// y2 * sin2 (q3 is freed by this time)(part of d1)
392 smull v24.4s, v6.4h, v0.4h[1] //// y1 * cos1(part of b0)
394 smull v26.4s, v6.4h, v0.4h[3] //// y1 * cos3(part of b1)
396 smull v28.4s, v6.4h, v1.4h[1] //// y1 * sin3(part of b2)
398 smull v30.4s, v6.4h, v1.4h[3] //// y1 * sin1(part of b3)
408 smull v22.4s, v10.4h, v0.4h[0] //// y4 * cos4(part of c0 and c1)
410 smull v6.4s, v3.4h, v0.4h[2] //// y2 * cos2(part of d0)
505 smull v24.4s, v6.4h, v0.4h[1] //// y1 * cos1(part of b0)
506 smull v26.4s, v6.4h, v0.4h[3] //// y1 * cos3(part of b1)
[all …]
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| /external/llvm/test/CodeGen/ARM/ |
| D | mulhi.ll | 10 ; V4: smull
13 ; M3: smull
45 ; V4: smull
49 ; M3: smull
|
| D | 2007-05-14-RegScavengerAssert.ll | 24 …%tmp81 = call i32 asm "smull $0, $1, $2, $3 \0A\09mov $0, $0, lsr $4\0A\09add $1, $0, …
25 …%tmp90 = call i32 asm "smull $0, $1, $2, $3 \0A\09mov $0, $0, lsr $4\0A\09add $1, $0, …
|
| /external/llvm/test/Transforms/InstCombine/ |
| D | 2012-04-23-Neon-Intrinsics.ll | 71 …%a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> zeroinitializer) n…
79 …%a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> <i16 1, i16 1, i16…
88 …%a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4…
96 …%b = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>…
112 …%a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4…
116 ; CHECK-NEXT: %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 …
122 …%a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4…
130 declare <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
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| /external/libavc/common/armv8/ |
| D | ih264_iquant_itrans_recon_av8.s | 145 smull v0.4s, v16.4h, v20.4h // q0 = p[i] = (x[i] * trns_coeff[i]) where i = 0..3
146 smull v2.4s, v17.4h, v21.4h // q1 = p[i] = (x[i] * trns_coeff[i]) where i = 4..7
147 smull v4.4s, v18.4h, v22.4h // q2 = p[i] = (x[i] * trns_coeff[i]) where i = 8..11
148 smull v6.4s, v19.4h, v23.4h // q3 = p[i] = (x[i] * trns_coeff[i]) where i = 12..15
336 smull v0.4s, v16.4h, v20.4h // q0 = p[i] = (x[i] * trns_coeff[i]) where i = 0..3
337 smull v2.4s, v17.4h, v21.4h // q1 = p[i] = (x[i] * trns_coeff[i]) where i = 4..7
338 smull v4.4s, v18.4h, v22.4h // q2 = p[i] = (x[i] * trns_coeff[i]) where i = 8..11
339 smull v6.4s, v19.4h, v23.4h // q3 = p[i] = (x[i] * trns_coeff[i]) where i = 12..15
554 smull v16.4s, v0.4h, v8.4h
556 smull v18.4s, v1.4h, v9.4h
[all …]
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| D | ih264_resi_trans_quant_av8.s | 193 smull v0.4s, v0.4h, v28.4h //multiply and add row 1
194 smull v1.4s, v1.4h, v29.4h //multiply and add row 2
195 smull v2.4s, v2.4h, v30.4h //multiply and add row 3
196 smull v3.4s, v3.4h, v31.4h //multiply and add row 4
416 smull v0.4s, v0.4h, v28.4h //multiply and add row 1
417 smull v1.4s, v1.4h, v29.4h //multiply and add row 2
418 smull v2.4s, v2.4h, v30.4h //multiply and add row 3
419 smull v3.4s, v3.4h, v31.4h //multiply and add row 4
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| D | ih264_iquant_itrans_recon_dc_av8.s | 139 smull v0.4s, v0.4h, v2.4h
351 smull v0.4s, v0.4h, v1.4h
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| D | ih264_intra_pred_chroma_av8.s | 451 smull v22.4s, v14.4h, v18.4h
452 smull v24.4s, v15.4h, v18.4h
453 smull v26.4s, v16.4h, v18.4h
454 smull v28.4s, v17.4h, v18.4h
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| /external/llvm/test/CodeGen/AArch64/ |
| D | aarch64-smull.ll | 5 ; CHECK: smull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
16 ; CHECK: smull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
27 ; CHECK: smull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
228 ; CHECK: smull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
246 ; CHECK: smull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
254 ; CHECK: smull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
295 ; If one operand has a zero-extend and the other a sign-extend, smull
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| D | arm64-vmul.ll | 6 ;CHECK: smull.8h
9 %tmp3 = call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
15 ;CHECK: smull.4s
18 %tmp3 = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
24 ;CHECK: smull.2d
27 %tmp3 = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
31 declare <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
32 declare <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
33 declare <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
260 %tmp4 = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
[all …]
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| D | arm64-neon-2velem.ll | 41 declare <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32>, <2 x i32>)
43 declare <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16>, <4 x i16>)
566 %vmull2.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %b, <4 x i16> %shuffle)
577 %vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %b, <2 x i32> %shuffle)
588 %vmull2.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %b, <4 x i16> %shuffle)
599 %vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %b, <2 x i32> %shuffle)
611 …%vmull2.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i, <4 x i16> %sh…
623 …%vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i, <2 x i32> %sh…
635 …%vmull2.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i, <4 x i16> %sh…
647 …%vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i, <2 x i32> %sh…
[all …]
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| D | arm64-neon-2velem-high.ll | 23 declare <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32>, <2 x i32>)
25 declare <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16>, <4 x i16>)
37 …%vmull15.i.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16…
49 …%vmull9.i.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32>…
115 …%vmull2.i.i.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i1…
128 …%vmull2.i.i.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i3…
196 …%vmull2.i.i.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i1…
208 …%vmull2.i.i.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i3…
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| /external/llvm/test/MC/AArch64/ |
| D | neon-2velem.s | 203 smull v0.4s, v1.4h, v2.h[2]
204 smull v0.2d, v1.2s, v2.s[2]
205 smull v0.2d, v1.2s, v22.s[2]
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| /external/llvm/test/MC/ARM/ |
| D | directive-arch-armv4.s | 34 smull r4, r5, r6, r3
|