| /external/llvm/test/MC/AArch64/ |
| D | neon-saturating-shift.s | 9 sqshl v0.8b, v1.8b, v2.8b
10 sqshl v0.16b, v1.16b, v2.16b
11 sqshl v0.4h, v1.4h, v2.4h
12 sqshl v0.8h, v1.8h, v2.8h
13 sqshl v0.2s, v1.2s, v2.2s
14 sqshl v0.4s, v1.4s, v2.4s
15 sqshl v0.2d, v1.2d, v2.2d
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| D | neon-scalar-saturating-shift.s | 6 sqshl b0, b1, b2
7 sqshl h10, h11, h12
8 sqshl s20, s21, s2
9 sqshl d17, d31, d8
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| D | neon-scalar-shift-imm.s | 71 sqshl b11, b19, #7
72 sqshl h13, h18, #11
73 sqshl s14, s17, #22
74 sqshl d15, d16, #51
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| D | neon-simd-shift.s | 221 sqshl v0.8b, v1.8b, #3
222 sqshl v0.4h, v1.4h, #3
223 sqshl v0.2s, v1.2s, #3
224 sqshl v0.16b, v1.16b, #3
225 sqshl v0.8h, v1.8h, #3
226 sqshl v0.4s, v1.4s, #3
227 sqshl v0.2d, v1.2d, #3
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| D | arm64-advsimd.s | 350 sqshl.8b v0, v0, v0
421 ; CHECK: sqshl.8b v0, v0, v0 ; encoding: [0x00,0x4c,0x20,0x0e]
1213 sqshl b0, b0, #1
1214 sqshl h0, h0, #2
1215 sqshl s0, s0, #3
1216 sqshl d0, d0, #4 define
1262 ; CHECK: sqshl b0, b0, #1 ; encoding: [0x00,0x74,0x09,0x5f]
1263 ; CHECK: sqshl h0, h0, #2 ; encoding: [0x00,0x74,0x12,0x5f]
1264 ; CHECK: sqshl s0, s0, #3 ; encoding: [0x00,0x74,0x23,0x5f]
1265 ; CHECK: sqshl d0, d0, #4 ; encoding: [0x00,0x74,0x44,0x5f]
[all …]
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| D | neon-diagnostics.s | 929 sqshl v0.2s, v15.4s, v16.2d
986 sqshl b0, s1, b0
988 sqshl s0, h1, s0
1741 sqshl v0.8b, v1.8h, #3
1742 sqshl v0.4h, v1.4s, #3
1743 sqshl v0.2s, v1.2d, #3
1744 sqshl v0.16b, v1.16b, #8
1745 sqshl v0.8h, v1.8h, #16
1746 sqshl v0.4s, v1.4s, #32
1747 sqshl v0.2d, v1.2d, #64
[all …]
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-sqshl-uqshl-i64Contant.ll | 3 ; Check if sqshl/uqshl with constant shift amout can be selected.
6 ; CHECK: sqshl {{d[0-9]+}}, {{d[0-9]+}}, #36
7 %1 = tail call i64 @llvm.aarch64.neon.sqshl.i64(i64 %a, i64 36)
19 declare i64 @llvm.aarch64.neon.sqshl.i64(i64, i64)
|
| D | arm64-vshift.ll | 5 ;CHECK: sqshl.8b
8 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
14 ;CHECK: sqshl.4h
17 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
23 ;CHECK: sqshl.2s
26 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
59 ;CHECK: sqshl.16b
62 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
68 ;CHECK: sqshl.8h
71 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
[all …]
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | neon-instructions.txt | 400 # CHECK: sqshl v1.8b, v15.8b, v22.8b
402 # CHECK: sqshl v3.4h, v13.4h, v24.4h
404 # CHECK: sqshl v5.2s, v11.2s, v26.2s
462 # CHECK: sqshl d31, d31, d31
464 # CHECK: sqshl h3, h4, h15
918 # CHECK: sqshl v0.8b, v1.8b, #3
919 # CHECK: sqshl v0.4h, v1.4h, #3
920 # CHECK: sqshl v0.2s, v1.2s, #3
921 # CHECK: sqshl v0.16b, v1.16b, #3
922 # CHECK: sqshl v0.8h, v1.8h, #3
[all …]
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| D | arm64-advsimd.txt | 333 # CHECK: sqshl.8b v0, v0, v0
1819 # CHECK: sqshl b0, b0, #1
1820 # CHECK: sqshl h0, h0, #2
1821 # CHECK: sqshl s0, s0, #3
1822 # CHECK: sqshl d0, d0, #4
2080 # CHECK: sqshl.8b v0, v0, #1
2081 # CHECK: sqshl.16b v0, v0, #2
2082 # CHECK: sqshl.4h v0, v0, #3
2083 # CHECK: sqshl.8h v0, v0, #4
2084 # CHECK: sqshl.2s v0, v0, #5
[all …]
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| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.stdout.exp | 28064 sqshl d1, d2, d4 0d6aae12a4d5779ab5a5b48f1015ae1b c971f3a936d96d74a62a62f4fad7e5b8 b9a3e85c054f…
28065 sqshl s1, s2, s4 a3f2079bdd17a30978caf3dcfb755f76 37054689934a896f9df4aa35ac689d65 7800c5c86edd…
28066 sqshl h1, h2, h4 5ed6b7499358f82ba684069f577ce6c5 6024148da208923bd4c22b2c452d3063 0896c3d63f84…
28067 sqshl b1, b2, b4 43ac209289e99934c3e8cfcf68fde6bc 4962c3292764af0cd0a9c9cc09fa4267 6efa48fa3d99…
28080 sqshl v1.2d, v2.2d, v4.2d 5396ed5e3f159dbf186b49bc2d39f392 a0ed54e326dd81be1a34375a77eee17a 2…
28081 sqshl v1.4s, v2.4s, v4.4s 583a2ed3f1623276e641c6b96b84f619 4ca28ea81c0d7c0bc2617186808642fc 5…
28082 sqshl v1.2s, v2.2s, v4.2s 21006aa4644157dc897fb4ca7c9cac28 922da94a93f0f544a78d2dedf9f62f64 5…
28083 sqshl v1.8h, v2.8h, v4.8h 8a12b45e3bb4d200ef6ed788568cd64d 9642cae1de73ee56e066fc307d3ef4ca 1…
28084 sqshl v1.4h, v2.4h, v4.4h afb60e2b82552f30d296ebd5c8ba366d 5fd3e1be4514ae3b24f53e0b134e2f44 4…
28085 sqshl v1.16b, v2.16b, v4.16b 87bd1a34f39932c9ee9b70ef99742876 f27652568c275b27f64ed771fef78386 …
[all …]
|
| /external/vixl/test/ |
| D | test-simulator-a64.cc | 3710 DEFINE_TEST_NEON_3SAME(sqshl, Basic)
3787 DEFINE_TEST_NEON_3SAME_SCALAR(sqshl, Basic)
3867 DEFINE_TEST_NEON_2OPIMM(sqshl, Basic, TypeWidthFromZero) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
3900 DEFINE_TEST_NEON_2OPIMM_SCALAR(sqshl, Basic, TypeWidthFromZero) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
|
| /external/vixl/src/vixl/a64/ |
| D | macro-assembler-a64.h | 2158 V(sqshl, Sqshl) \
2381 V(sqshl, Sqshl) \
|
| D | assembler-a64.h | 2478 void sqshl(const VRegister& vd,
2845 void sqshl(const VRegister& vd,
|
| D | simulator-a64.cc | 3720 case NEON_SQSHL_imm_scalar: sqshl(vf, rd, rn, left_shift); break; in VisitNEONScalarShiftImmediate()
3794 case NEON_SQSHL_imm: sqshl(vf, rd, rn, left_shift); break; in VisitNEONShiftImmediate()
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| D | simulator-a64.h | 2141 LogicVRegister sqshl(VectorFormat vform,
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| D | assembler-a64.cc | 3219 V(sqshl, NEON_SQSHL, true) \
4203 void Assembler::sqshl(const VRegister& vd, in sqshl() function in vixl::Assembler
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| D | logic-a64.cc | 1693 LogicVRegister Simulator::sqshl(VectorFormat vform, in sqshl() function in vixl::Simulator
|
| /external/vixl/doc/ |
| D | supported-instructions.md | 3501 void sqshl(const VRegister& vd,
3510 void sqshl(const VRegister& vd,
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2773 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>;
3004 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>;
4424 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4473 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
|