/external/libhevc/decoder/arm64/ |
D | ihevcd_fmt_conv_420sp_to_rgba8888.s | 213 sqshrn2 v5.8h, v7.4s,#13 ////D9 = (U-128)*C4>>13 4 16-BIT VALUES 218 sqshrn2 v7.8h, v22.4s,#13 ////D11 = (V-128)*C1>>13 4 16-BIT VALUES 223 sqshrn2 v12.8h, v14.4s,#13 ////D13 = [(U-128)*C2 + (V-128)*C3]>>13 4 16-BIT VALUES 376 sqshrn2 v5.8h, v7.4s,#13 ////D9 = (U-128)*C4>>13 4 16-BIT VALUES 381 sqshrn2 v7.8h, v22.4s,#13 ////D11 = (V-128)*C1>>13 4 16-BIT VALUES 386 sqshrn2 v12.8h, v14.4s,#13 ////D13 = [(U-128)*C2 + (V-128)*C3]>>13 4 16-BIT VALUES
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/external/llvm/test/MC/AArch64/ |
D | neon-simd-shift.s | 335 sqshrn2 v0.16b, v1.8h, #3 336 sqshrn2 v0.8h, v1.4s, #3 337 sqshrn2 v0.4s, v1.2d, #3
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D | arm64-advsimd.s | 1362 sqshrn2.16b v0, v0, #2 1364 sqshrn2.8h v0, v0, #4 1366 sqshrn2.4s v0, v0, #6 1534 ; CHECK: sqshrn2.16b v0, v0, #2 ; encoding: [0x00,0x94,0x0e,0x4f] 1536 ; CHECK: sqshrn2.8h v0, v0, #4 ; encoding: [0x00,0x94,0x1c,0x4f] 1538 ; CHECK: sqshrn2.4s v0, v0, #6 ; encoding: [0x00,0x94,0x3a,0x4f] 1669 sqshrn2 v8.16b, v9.8h, #2 1671 sqshrn2 v6.8h, v7.4s, #4 1673 sqshrn2 v4.4s, v5.2d, #6 1737 ; CHECK: sqshrn2.16b v8, v9, #2 ; encoding: [0x28,0x95,0x0e,0x4f] [all …]
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D | neon-diagnostics.s | 1926 sqshrn2 v0.16b, v1.8h, #17 1927 sqshrn2 v0.8h, v1.4s, #33 1928 sqshrn2 v0.4s, v1.2d, #65
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/external/llvm/test/CodeGen/AArch64/ |
D | arm64-neon-simd-shift.ll | 434 ; CHECK: sqshrn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, #3 445 ; CHECK: sqshrn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, #9 456 ; CHECK: sqshrn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, #19
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D | arm64-vshift.ll | 775 ;CHECK: sqshrn2.16b v0, {{v[0-9]+}}, #1 785 ;CHECK: sqshrn2.8h v0, {{v[0-9]+}}, #1 795 ;CHECK: sqshrn2.4s v0, {{v[0-9]+}}, #1
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/external/llvm/test/MC/Disassembler/AArch64/ |
D | arm64-advsimd.txt | 2088 # CHECK: sqshrn2.16b v0, v0, #6 2090 # CHECK: sqshrn2.8h v0, v0, #12 2092 # CHECK: sqshrn2.4s v0, v0, #26
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D | neon-instructions.txt | 1021 # CHECK: sqshrn2 v0.16b, v1.8h, #3 1022 # CHECK: sqshrn2 v0.8h, v1.4s, #3 1023 # CHECK: sqshrn2 v0.4s, v1.2d, #3
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/external/valgrind/none/tests/arm64/ |
D | fp_and_simd.stdout.exp | 28203 sqshrn2 v4.4s, v29.2d, #1 cefc25239f4fc109228f75320c51a63b fb15d7a5f5fdf51b76529eba842141c2 80… 28204 sqshrn2 v4.4s, v29.2d, #17 01cb12f62a9ed61ba03220cb14ba3ff3 830a4075a8ff75c3c76cbafa617fe929 8… 28205 sqshrn2 v4.4s, v29.2d, #32 6f263492fa6d9a19ce2554529627997b e083b647b8f8fc0f60cf375fd157ac18 e… 28210 sqshrn2 v4.8h, v29.4s, #1 fb9445656f1cf9c7de9cf637db751c3b 121a87201e02d5260cb36deebb043da3 7f… 28211 sqshrn2 v4.8h, v29.4s, #9 32d00c123985c581194473835c10e3f2 2f4cdb1ba1ee1bc5a9a26c30a163235a 7f… 28212 sqshrn2 v4.8h, v29.4s, #16 e4d948ca89ac7f66437db9fd96eeacba 60437a57c210a848ce1a0bd9597c64d8 6… 28216 sqshrn2 v4.16b, v29.8h, #1 6350755ee93f1abc2bd34bf5e5ae6e21 6dadd3d3d220e862a02361ef80f55056 7f… 28217 sqshrn2 v4.16b, v29.8h, #4 3a616265b4e5d51d62bdc989e9c73ad9 66bab0fa13eda9fdaee7da6eebbe08df 7f… 28218 sqshrn2 v4.16b, v29.8h, #8 f21156b08b9aa1b38418e9017d0b161b f9a50437562884dda74dcf00174a1904 f9…
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/external/vixl/src/vixl/a64/ |
D | simulator-a64.h | 2225 LogicVRegister sqshrn2(VectorFormat vform,
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D | macro-assembler-a64.h | 2384 V(sqshrn2, Sqshrn2) \
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D | assembler-a64.h | 3261 void sqshrn2(const VRegister& vd,
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D | simulator-a64.cc | 3846 sqshrn2(vf, rd, rn, right_shift); in VisitNEONShiftImmediate()
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D | logic-a64.cc | 2697 LogicVRegister Simulator::sqshrn2(VectorFormat vform, in sqshrn2() function in vixl::Simulator
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D | assembler-a64.cc | 4392 void Assembler::sqshrn2(const VRegister& vd, in sqshrn2() function in vixl::Assembler
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/external/vixl/doc/ |
D | supported-instructions.md | 3537 void sqshrn2(const VRegister& vd,
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