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/external/libvpx/libvpx/vpx_dsp/mips/
Dvpx_convolve_copy_msa.c18 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; in copy_width8_msa() local
22 LD_UB8(src, src_stride, src0, src1, src2, src3, src4, src5, src6, src7); in copy_width8_msa()
25 out0 = __msa_copy_u_d((v2i64)src0, 0); in copy_width8_msa()
39 LD_UB4(src, src_stride, src0, src1, src2, src3); in copy_width8_msa()
42 out0 = __msa_copy_u_d((v2i64)src0, 0); in copy_width8_msa()
51 LD_UB8(src, src_stride, src0, src1, src2, src3, src4, src5, src6, src7); in copy_width8_msa()
54 out0 = __msa_copy_u_d((v2i64)src0, 0); in copy_width8_msa()
70 LD_UB4(src, src_stride, src0, src1, src2, src3); in copy_width8_msa()
72 out0 = __msa_copy_u_d((v2i64)src0, 0); in copy_width8_msa()
82 LD_UB2(src, src_stride, src0, src1); in copy_width8_msa()
[all …]
Dvariance_msa.c43 uint32_t src0, src1, src2, src3; in sse_diff_4width_msa() local
52 LW4(src_ptr, src_stride, src0, src1, src2, src3); in sse_diff_4width_msa()
57 INSERT_W4_UB(src0, src1, src2, src3, src); in sse_diff_4width_msa()
72 v16u8 src0, src1, src2, src3; in sse_diff_8width_msa() local
78 LD_UB4(src_ptr, src_stride, src0, src1, src2, src3); in sse_diff_8width_msa()
83 PCKEV_D4_UB(src1, src0, src3, src2, ref1, ref0, ref3, ref2, in sse_diff_8width_msa()
84 src0, src1, ref0, ref1); in sse_diff_8width_msa()
85 CALC_MSE_AVG_B(src0, ref0, var, avg); in sse_diff_8width_msa()
139 v16u8 src0, src1, ref0, ref1; in sse_diff_32width_msa() local
144 LD_UB2(src_ptr, 16, src0, src1); in sse_diff_32width_msa()
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Dvpx_convolve8_horiz_msa.c19 v16i8 src0, src1, src2, src3, filt0, filt1, filt2, filt3; in common_hz_8t_4x4_msa() local
33 LD_SB4(src, src_stride, src0, src1, src2, src3); in common_hz_8t_4x4_msa()
34 XORI_B4_128_SB(src0, src1, src2, src3); in common_hz_8t_4x4_msa()
35 HORIZ_8TAP_4WID_4VECS_FILT(src0, src1, src2, src3, mask0, mask1, mask2, mask3, in common_hz_8t_4x4_msa()
47 v16i8 src0, src1, src2, src3; in common_hz_8t_4x8_msa() local
62 LD_SB4(src, src_stride, src0, src1, src2, src3); in common_hz_8t_4x8_msa()
63 XORI_B4_128_SB(src0, src1, src2, src3); in common_hz_8t_4x8_msa()
65 HORIZ_8TAP_4WID_4VECS_FILT(src0, src1, src2, src3, mask0, mask1, mask2, mask3, in common_hz_8t_4x8_msa()
67 LD_SB4(src, src_stride, src0, src1, src2, src3); in common_hz_8t_4x8_msa()
68 XORI_B4_128_SB(src0, src1, src2, src3); in common_hz_8t_4x8_msa()
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Dsub_pixel_variance_msa.c52 uint32_t src0, src1, src2, src3; in avg_sse_diff_4width_msa() local
62 LW4(src_ptr, src_stride, src0, src1, src2, src3); in avg_sse_diff_4width_msa()
67 INSERT_W4_UB(src0, src1, src2, src3, src); in avg_sse_diff_4width_msa()
88 v16u8 src0, src1, src2, src3; in avg_sse_diff_8width_msa() local
97 LD_UB4(src_ptr, src_stride, src0, src1, src2, src3); in avg_sse_diff_8width_msa()
102 PCKEV_D4_UB(src1, src0, src3, src2, ref1, ref0, ref3, ref2, in avg_sse_diff_8width_msa()
103 src0, src1, ref0, ref1); in avg_sse_diff_8width_msa()
104 AVER_UB2_UB(src0, pred0, src1, pred1, src0, src1); in avg_sse_diff_8width_msa()
105 CALC_MSE_AVG_B(src0, ref0, var, avg); in avg_sse_diff_8width_msa()
179 v16u8 src0, src1, ref0, ref1, pred0, pred1; in avg_sse_diff_32width_msa() local
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Dsad_msa.c26 uint32_t src0, src1, src2, src3, ref0, ref1, ref2, ref3; in sad_4width_msa() local
33 LW4(src_ptr, src_stride, src0, src1, src2, src3); in sad_4width_msa()
38 INSERT_W4_UB(src0, src1, src2, src3, src); in sad_4width_msa()
52 v16u8 src0, src1, src2, src3, ref0, ref1, ref2, ref3; in sad_8width_msa() local
56 LD_UB4(src, src_stride, src0, src1, src2, src3); in sad_8width_msa()
61 PCKEV_D4_UB(src1, src0, src3, src2, ref1, ref0, ref3, ref2, in sad_8width_msa()
62 src0, src1, ref0, ref1); in sad_8width_msa()
63 sad += SAD_UB2_UH(src0, src1, ref0, ref1); in sad_8width_msa()
73 v16u8 src0, src1, ref0, ref1; in sad_16width_msa() local
77 LD_UB2(src, src_stride, src0, src1); in sad_16width_msa()
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Dvpx_convolve8_avg_horiz_msa.c20 v16i8 src0, src1, src2, src3, filt0, filt1, filt2, filt3; in common_hz_8t_and_aver_dst_4x4_msa() local
36 LD_SB4(src, src_stride, src0, src1, src2, src3); in common_hz_8t_and_aver_dst_4x4_msa()
37 XORI_B4_128_SB(src0, src1, src2, src3); in common_hz_8t_and_aver_dst_4x4_msa()
38 HORIZ_8TAP_4WID_4VECS_FILT(src0, src1, src2, src3, mask0, mask1, mask2, mask3, in common_hz_8t_and_aver_dst_4x4_msa()
55 v16i8 src0, src1, src2, src3, filt0, filt1, filt2, filt3; in common_hz_8t_and_aver_dst_4x8_msa() local
71 LD_SB4(src, src_stride, src0, src1, src2, src3); in common_hz_8t_and_aver_dst_4x8_msa()
72 XORI_B4_128_SB(src0, src1, src2, src3); in common_hz_8t_and_aver_dst_4x8_msa()
75 HORIZ_8TAP_4WID_4VECS_FILT(src0, src1, src2, src3, mask0, mask1, mask2, mask3, in common_hz_8t_and_aver_dst_4x8_msa()
77 LD_SB4(src, src_stride, src0, src1, src2, src3); in common_hz_8t_and_aver_dst_4x8_msa()
78 XORI_B4_128_SB(src0, src1, src2, src3); in common_hz_8t_and_aver_dst_4x8_msa()
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Dvpx_convolve_msa.h32 #define HORIZ_8TAP_FILT(src0, src1, mask0, mask1, mask2, mask3, \ argument
37 VSHF_B4_SB(src0, src1, mask0, mask1, mask2, mask3, \
48 #define HORIZ_8TAP_4WID_4VECS_FILT(src0, src1, src2, src3, \ argument
55 VSHF_B2_SB(src0, src1, src2, src3, mask0, mask0, vec0_m, vec1_m); \
57 VSHF_B2_SB(src0, src1, src2, src3, mask1, mask1, vec2_m, vec3_m); \
59 VSHF_B2_SB(src0, src1, src2, src3, mask2, mask2, vec4_m, vec5_m); \
61 VSHF_B2_SB(src0, src1, src2, src3, mask3, mask3, vec6_m, vec7_m); \
66 #define HORIZ_8TAP_8WID_4VECS_FILT(src0, src1, src2, src3, \ argument
73 VSHF_B2_SB(src0, src0, src1, src1, mask0, mask0, vec0_m, vec1_m); \
77 VSHF_B2_SB(src0, src0, src1, src1, mask2, mask2, vec0_m, vec1_m); \
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Dvpx_convolve_avg_msa.c17 v16u8 src0, src1, src2, src3; in avg_width4_msa() local
22 LD_UB4(src, src_stride, src0, src1, src2, src3); in avg_width4_msa()
27 AVER_UB4_UB(src0, dst0, src1, dst1, src2, dst2, src3, dst3, in avg_width4_msa()
39 LD_UB2(src, src_stride, src0, src1); in avg_width4_msa()
44 AVER_UB2_UB(src0, dst0, src1, dst1, dst0, dst1); in avg_width4_msa()
60 v16u8 src0, src1, src2, src3; in avg_width8_msa() local
64 LD_UB4(src, src_stride, src0, src1, src2, src3); in avg_width8_msa()
68 AVER_UB4_UB(src0, dst0, src1, dst1, src2, dst2, src3, dst3, in avg_width8_msa()
83 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; in avg_width16_msa() local
87 LD_UB8(src, src_stride, src0, src1, src2, src3, src4, src5, src6, src7); in avg_width16_msa()
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Dvpx_convolve8_vert_msa.c19 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10; in common_vt_8t_4w_msa() local
31 LD_SB7(src, src_stride, src0, src1, src2, src3, src4, src5, src6); in common_vt_8t_4w_msa()
34 ILVR_B4_SB(src1, src0, src3, src2, src5, src4, src2, src1, src10_r, src32_r, in common_vt_8t_4w_msa()
70 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10; in common_vt_8t_8w_msa() local
81 LD_SB7(src, src_stride, src0, src1, src2, src3, src4, src5, src6); in common_vt_8t_8w_msa()
82 XORI_B7_128_SB(src0, src1, src2, src3, src4, src5, src6); in common_vt_8t_8w_msa()
84 ILVR_B4_SB(src1, src0, src3, src2, src5, src4, src2, src1, src10_r, src32_r, in common_vt_8t_8w_msa()
124 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10; in common_vt_8t_16w_msa() local
137 LD_SB7(src, src_stride, src0, src1, src2, src3, src4, src5, src6); in common_vt_8t_16w_msa()
138 XORI_B7_128_SB(src0, src1, src2, src3, src4, src5, src6); in common_vt_8t_16w_msa()
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Dvpx_convolve8_avg_vert_msa.c22 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10; in common_vt_8t_and_aver_dst_4w_msa() local
34 LD_SB7(src, src_stride, src0, src1, src2, src3, src4, src5, src6); in common_vt_8t_and_aver_dst_4w_msa()
37 ILVR_B4_SB(src1, src0, src3, src2, src5, src4, src2, src1, src10_r, src32_r, in common_vt_8t_and_aver_dst_4w_msa()
82 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10; in common_vt_8t_and_aver_dst_8w_msa() local
93 LD_SB7(src, src_stride, src0, src1, src2, src3, src4, src5, src6); in common_vt_8t_and_aver_dst_8w_msa()
96 XORI_B7_128_SB(src0, src1, src2, src3, src4, src5, src6); in common_vt_8t_and_aver_dst_8w_msa()
97 ILVR_B4_SB(src1, src0, src3, src2, src5, src4, src2, src1, src10_r, src32_r, in common_vt_8t_and_aver_dst_8w_msa()
143 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10; in common_vt_8t_and_aver_dst_16w_mult_msa() local
160 LD_SB7(src_tmp, src_stride, src0, src1, src2, src3, src4, src5, src6); in common_vt_8t_and_aver_dst_16w_mult_msa()
161 XORI_B7_128_SB(src0, src1, src2, src3, src4, src5, src6); in common_vt_8t_and_aver_dst_16w_mult_msa()
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/external/mesa3d/src/gallium/auxiliary/gallivm/
Dlp_bld_tgsi_aos.c460 LLVMValueRef src0, src1, src2; in lp_emit_instruction_aos() local
484 src0 = lp_build_emit_fetch(&bld->bld_base, inst, 0, LP_CHAN_ALL); in lp_emit_instruction_aos()
485 dst0 = lp_build_floor(&bld->bld_base.base, src0); in lp_emit_instruction_aos()
497 src0 = lp_build_emit_fetch(&bld->bld_base, inst, 0, LP_CHAN_ALL); in lp_emit_instruction_aos()
498 dst0 = lp_build_rcp(&bld->bld_base.base, src0); in lp_emit_instruction_aos()
503 src0 = lp_build_emit_fetch(&bld->bld_base, inst, 0, LP_CHAN_ALL); in lp_emit_instruction_aos()
504 tmp0 = lp_build_emit_llvm_unary(&bld->bld_base, TGSI_OPCODE_ABS, src0); in lp_emit_instruction_aos()
515 src0 = lp_build_emit_fetch(&bld->bld_base, inst, 0, LP_CHAN_ALL); in lp_emit_instruction_aos()
517 dst0 = lp_build_mul(&bld->bld_base.base, src0, src1); in lp_emit_instruction_aos()
521 src0 = lp_build_emit_fetch(&bld->bld_base, inst, 0, LP_CHAN_ALL); in lp_emit_instruction_aos()
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/external/mesa3d/src/gallium/drivers/radeon/
DR600Instructions.td92 (ins R600_Reg32:$src0, R600_Reg32:$src1,R600_Pred:$p, variable_ops),
93 !strconcat(opName, " $dst, $src0, $src1"),
102 (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2,R600_Pred:$p, variable_ops),
103 !strconcat(opName, " $dst, $src0, $src1, $src2"),
113 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),
114 "PRED $dst, $src0, $src1",
117 let DisableEncoding = "$src0";
149 (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2),
150 !strconcat(opName, "$dst, $src0, $src1, $src2"),
243 [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))]
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DAMDGPUInstructions.td98 (ins rc:$src0),
99 "CLAMP $dst, $src0",
100 [(set rc:$dst, (int_AMDIL_clamp rc:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
105 (ins rc:$src0),
106 "FABS $dst, $src0",
107 [(set rc:$dst, (fabs rc:$src0))]
112 (ins rc:$src0),
113 "FNEG $dst, $src0",
114 [(set rc:$dst, (fneg rc:$src0))]
124 (int_AMDGPU_pow rc:$src0, rc:$src1),
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DSIInstrFormats.td26 …: VOP3 <op, (outs VReg_32:$dst), (ins AllReg_32:$src0, AllReg_32:$src1, AllReg_32:$src2, i32imm:$s…
29 …: VOP3 <op, (outs VReg_64:$dst), (ins AllReg_64:$src0, AllReg_64:$src1, AllReg_64:$src2, i32imm:$s…
33 : SOP1 <op, (outs SReg_32:$dst), (ins SReg_32:$src0), opName, pattern>;
36 : SOP1 <op, (outs SReg_64:$dst), (ins SReg_64:$src0), opName, pattern>;
39 : SOP2 <op, (outs SReg_32:$dst), (ins SReg_32:$src0, SReg_32:$src1), opName, pattern>;
42 : SOP2 <op, (outs SReg_64:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
45 : SOP2 <op, (outs VCCReg:$vcc), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
50 op, (outs vrc:$dst), (ins arc:$src0), opName, pattern
73 op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern
95 : SOPK <op, (outs SReg_32:$dst), (ins i16imm:$src0), opName, pattern>;
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/external/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_exec.c114 const union tgsi_exec_channel *src0, in micro_clamp() argument
118 …dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[… in micro_clamp()
119 …dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[… in micro_clamp()
120 …dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[… in micro_clamp()
121 …dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[… in micro_clamp()
126 const union tgsi_exec_channel *src0, in micro_cmp() argument
130 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0]; in micro_cmp()
131 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1]; in micro_cmp()
132 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2]; in micro_cmp()
133 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3]; in micro_cmp()
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/external/mesa3d/src/gallium/docs/source/
Dtgsi.rst15 registers, called *src0* through *src2*, or simply *src* if there is only
122 dst.x = src0.x \times src1.x
124 dst.y = src0.y \times src1.y
126 dst.z = src0.z \times src1.z
128 dst.w = src0.w \times src1.w
135 dst.x = src0.x + src1.x
137 dst.y = src0.y + src1.y
139 dst.z = src0.z + src1.z
141 dst.w = src0.w + src1.w
150 dst = src0.x \times src1.x + src0.y \times src1.y + src0.z \times src1.z
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/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_vec4.h163 src_reg src0 = src_reg(),
336 vec4_instruction *emit(enum opcode opcode, dst_reg dst, src_reg src0);
339 src_reg src0, src_reg src1);
342 src_reg src0, src_reg src1, src_reg src2);
347 vec4_instruction *MOV(dst_reg dst, src_reg src0);
348 vec4_instruction *NOT(dst_reg dst, src_reg src0);
349 vec4_instruction *RNDD(dst_reg dst, src_reg src0);
350 vec4_instruction *RNDE(dst_reg dst, src_reg src0);
351 vec4_instruction *RNDZ(dst_reg dst, src_reg src0);
352 vec4_instruction *FRC(dst_reg dst, src_reg src0);
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/external/mesa3d/src/gallium/drivers/svga/
Dsvga_tgsi_insn.c296 struct src_register *src0) in emit_repl() argument
303 src0_swizzle = src0->base.swizzle; in emit_repl()
312 src0->base.swizzle = SVGA3DSWIZZLE_NONE; in emit_repl()
314 if (!emit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, *src0 )) in emit_repl()
317 *src0 = src( dst ); in emit_repl()
318 src0->base.swizzle = src0_swizzle; in emit_repl()
335 struct src_register src0 ) in submit_op1() argument
337 return emit_op1( emit, inst, dest, src0 ); in submit_op1()
351 struct src_register src0, in submit_op2() argument
359 type0 = SVGA3dShaderGetRegType( src0.base.value ); in submit_op2()
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/external/libvpx/libvpx/vp8/common/mips/msa/
Dcopymem_msa.c17 uint64_t src0, src1, src2, src3; in copy_8x4_msa() local
19 LD4(src, src_stride, src0, src1, src2, src3); in copy_8x4_msa()
20 SD4(src0, src1, src2, src3, dst, dst_stride); in copy_8x4_msa()
26 uint64_t src0, src1, src2, src3; in copy_8x8_msa() local
28 LD4(src, src_stride, src0, src1, src2, src3); in copy_8x8_msa()
30 SD4(src0, src1, src2, src3, dst, dst_stride); in copy_8x8_msa()
33 LD4(src, src_stride, src0, src1, src2, src3); in copy_8x8_msa()
34 SD4(src0, src1, src2, src3, dst, dst_stride); in copy_8x8_msa()
40 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; in copy_16x16_msa() local
43 LD_UB8(src, src_stride, src0, src1, src2, src3, src4, src5, src6, src7); in copy_16x16_msa()
[all …]
Dsixtap_filter_msa.c37 #define HORIZ_6TAP_FILT(src0, src1, mask0, mask1, mask2, \ argument
43 VSHF_B3_SB(src0, src1, src0, src1, src0, src1, mask0, mask1, mask2, \
54 #define HORIZ_6TAP_4WID_4VECS_FILT(src0, src1, src2, src3, \ argument
61 VSHF_B2_SB(src0, src1, src2, src3, mask0, mask0, vec0_m, vec1_m); \
63 VSHF_B2_SB(src0, src1, src2, src3, mask1, mask1, vec2_m, vec3_m); \
65 VSHF_B2_SB(src0, src1, src2, src3, mask2, mask2, vec4_m, vec5_m); \
69 #define HORIZ_6TAP_8WID_4VECS_FILT(src0, src1, src2, src3, \ argument
76 VSHF_B2_SB(src0, src0, src1, src1, mask0, mask0, vec0_m, vec1_m); \
80 VSHF_B2_SB(src0, src0, src1, src1, mask1, mask1, vec0_m, vec1_m); \
82 VSHF_B2_SB(src0, src0, src1, src1, mask2, mask2, vec4_m, vec5_m); \
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Dbilinear_filter_msa.c41 v16i8 src0, src1, src2, src3, mask; in common_hz_2t_4x4_msa() local
50 LD_SB4(src, src_stride, src0, src1, src2, src3); in common_hz_2t_4x4_msa()
51 VSHF_B2_UB(src0, src1, src2, src3, mask, mask, vec0, vec1); in common_hz_2t_4x4_msa()
63 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, mask; in common_hz_2t_4x8_msa() local
72 LD_SB8(src, src_stride, src0, src1, src2, src3, src4, src5, src6, src7); in common_hz_2t_4x8_msa()
73 VSHF_B2_UB(src0, src1, src2, src3, mask, mask, vec0, vec1); in common_hz_2t_4x8_msa()
104 v16i8 src0, src1, src2, src3, mask; in common_hz_2t_8x4_msa() local
112 LD_SB4(src, src_stride, src0, src1, src2, src3); in common_hz_2t_8x4_msa()
113 VSHF_B2_UH(src0, src0, src1, src1, mask, mask, vec0, vec1); in common_hz_2t_8x4_msa()
118 PCKEV_B2_SB(vec1, vec0, vec3, vec2, src0, src1); in common_hz_2t_8x4_msa()
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/external/mesa3d/src/gallium/drivers/i915/
Di915_fpc_translate.c498 uint src0, src1, src2, flags; in i915_translate_instruction() local
503 src0 = src_vector(p, &inst->Src[0], fs); in i915_translate_instruction()
508 src0, negate(src0, 1, 1, 1, 1), 0); in i915_translate_instruction()
516 src0 = src_vector(p, &inst->Src[0], fs); in i915_translate_instruction()
523 negate(src0, 1, 1, 1, 1), 0, 0); in i915_translate_instruction()
532 src0 = src_vector(p, &inst->Src[0], fs); in i915_translate_instruction()
538 0, src0, src2, src1); /* NOTE: order of src2, src1 */ in i915_translate_instruction()
542 src0 = src_vector(p, &inst->Src[0], fs); in i915_translate_instruction()
548 src0, i915_emit_const1f(p, 1.0f / (float) (M_PI * 2.0)), 0); in i915_translate_instruction()
588 src0 = get_result_vector(p, &inst->Dst[0]); in i915_translate_instruction()
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/external/mesa3d/src/mesa/drivers/dri/i915/
Di915_fragprog.c409 GLuint src0, src1, src2, flags; in upload_program() local
414 src0 = src_vector(p, &inst->SrcReg[0], program); in upload_program()
419 src0, negate(src0, 1, 1, 1, 1), 0); in upload_program()
427 src0 = src_vector(p, &inst->SrcReg[0], program); in upload_program()
430 …i915_emit_arith(p, A0_CMP, get_result_vector(p, inst), get_result_flags(inst), 0, src0, src2, src1… in upload_program()
434 src0 = src_vector(p, &inst->SrcReg[0], program); in upload_program()
443 src0, in upload_program()
513 src0 = src_vector(p, &inst->SrcReg[0], program); in upload_program()
519 swizzle(src0, X, Y, ZERO, ZERO), in upload_program()
533 src0 = src_vector(p, &inst->SrcReg[0], program); in upload_program()
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/external/llvm/lib/Target/R600/
DEvergreenInstructions.td263 // [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
281 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))],
286 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))],
293 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))],
307 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))],
312 [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))], VecALU
331 [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))], VecALU
367 let src0 = 0;
427 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
430 " "#name#" $last OQAP, $src0$src0_rel $pred_sel",
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/external/opencv/cv/src/
Dcvderiv.cpp575 const int *src0 = src[-1], *src1 = src[0], *src2 = src[1]; in icvLaplaceCol_32s16s() local
580 int s0 = src0[i] - src1[i]*2 + src2[i] + src1[i+width]; in icvLaplaceCol_32s16s()
581 int s1 = src0[i+1] - src1[i+1]*2 + src2[i+1] + src1[i+width+1]; in icvLaplaceCol_32s16s()
586 dst[i] = (short)(src0[i] - src1[i]*2 + src2[i] + src1[i+width]); in icvLaplaceCol_32s16s()
591 int s0 = src0[i] - src1[i]*2 + src2[i] + in icvLaplaceCol_32s16s()
592 src0[i+width] + src1[i+width]*2 + src2[i+width]; in icvLaplaceCol_32s16s()
593 int s1 = src0[i+1] - src1[i+1]*2 + src2[i+1] + in icvLaplaceCol_32s16s()
594 src0[i+width+1] + src1[i+width+1]*2 + src2[i+width+1]; in icvLaplaceCol_32s16s()
600 int s0 = CV_DESCALE(src0[i] - src1[i]*2 + src2[i] + in icvLaplaceCol_32s16s()
601 src0[i+width] + src1[i+width]*2 + src2[i+width], 2); in icvLaplaceCol_32s16s()
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