| /external/llvm/test/CodeGen/AArch64/ |
| D | fast-isel-tbz.ll | 6 ; CHECK: tbz {{w[0-9]+}}, #0, {{LBB.+_2}}
18 ; CHECK: tbz w0, #1, {{LBB.+_2}}
30 ; CHECK: tbz w0, #2, {{LBB.+_2}}
42 ; CHECK: tbz w0, #3, {{LBB.+_2}}
54 ; CHECK: tbz x0, #32, {{LBB.+_2}}
170 ; FAST: tbz w0, #7, {{LBB.+_2}}
181 ; FAST: tbz w0, #15, {{LBB.+_2}}
236 ; FAST: tbz w0, #7, {{LBB.+_2}}
247 ; FAST: tbz w0, #15, {{LBB.+_2}}
258 ; CHECK: tbz w0, #31, {{LBB.+_2}}
[all …]
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| D | tst-br.ll | 18 ; CHECK: tbz {{w[0-9]+}}, #15, [[LBL_end1:.?LBB0_[0-9]+]]
24 ; CHECK: tbz {{w[0-9]+}}, #12, [[LBL_end1]]
30 ; CHECK: tbz {{[wx][0-9]+}}, #15, [[LBL_end1]]
36 ; CHECK: tbz {{[wx][0-9]+}}, #12, [[LBL_end1]]
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| D | tbz-tbnz.ll | 13 ; CHECK: tbz [[CMP]], #31
31 ; CHECK: tbz [[CMP]], #63
121 ; CHECK: tbz [[CMP]], #31
181 ; CHECK: tbz x0, #63
197 ; CHECK: tbz x0, #63
212 ; CHECK: tbz [[CMP]], #63
232 ; CHECK: tbz x0, #63
250 ; CHECK: tbz [[CMP]], #63
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| D | branch-relax-asm.ll | 1 ; RUN: llc -mtriple=aarch64-apple-ios7.0 -disable-block-placement -aarch64-tbz-offset-bits=4 -o - %…
7 ; of the limited range we gave tbz. So branch relaxation has to invert the
9 ; CHECK: tbz w0, #0, [[TRUE:LBB[0-9]+_[0-9]+]]
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| D | arm64-andCmpBrToTBZ.ll | 13 ; CHECK: tbz
39 ; CHECK: tbz
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| D | analyze-branch.ll | 171 ; CHECK: tbz {{[wx][0-9]+}}, #15, [[TRUE:.LBB[0-9]+_[0-9]+]]
194 ; CHECK: tbz {{w[0-9]+}}, #15, [[FALSE:.LBB[0-9]+_[0-9]+]]
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| D | fast-isel-cbz.ll | 5 ; CHECK: tbz w0, #0, {{LBB.+_2}}
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| D | directcond.ll | 44 ; CHECK: tbz {{w[0-9]+}}, #0, {{.?LBB}}
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| D | arm64-ccmp.ll | 76 ; Second block clobbers the flags and ends with a tbz terminator.
81 ; CHECK: tbz
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| /external/llvm/test/MC/AArch64/ |
| D | arm64-branch-encoding.s | 113 tbz x1, #3, foo
118 tbz w1, #3, foo
123 tbz w1, #3, #28
124 ; CHECK: tbz w1, #3, #28
125 tbz w3, #5, #32764
126 ; CHECK: tbz w3, #5, #32764 ; encoding: [0xe3,0xff,0x2b,0x36]
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| D | elf-reloc-tstb.s | 4 tbz x6, #45, somewhere
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| D | basic-a64-diagnostics.s | 3707 tbz w3, #-1, addr
3708 tbz w3, #32, nowhere
3709 tbz x9, #-1, there
3710 tbz x20, #64, dont
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| D | basic-a64-instructions.s | 4816 tbz x5, #0, somewhere
4817 tbz xzr, #63, elsewhere
4830 tbz w5, #12, anywhere
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-branch.txt | 54 # CHECK: tbz w0, #1, #16
56 # CHECK: tbz w1, #30, #-4
70 # CHECK: tbz w0, #1, #-12
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| /external/vixl/doc/topics/ |
| D | extending-the-disassembler.md | 52 VIXL disasm 0x7fff04cb05f0: tbz w10, #2, #-0x10 (addr 0x7fff04cb05e0)
53 custom disasm 0x8: tbz w10, #2, #-0x10 (addr -0x8)
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| /external/v8/test/cctest/ |
| D | test-disasm-arm64.cc | 817 COMPARE_PREFIX(tbz(w4, 0, INST_OFF(0x7ffc)), "tbz w4, #0, #+0x7ffc"); in TEST_()
818 COMPARE_PREFIX(tbz(x5, 63, INST_OFF(-0x8000)), "tbz x5, #63, #-0x8000"); in TEST_()
819 COMPARE_PREFIX(tbz(w6, 31, INST_OFF(0)), "tbz w6, #31, #+0x0"); in TEST_()
820 COMPARE_PREFIX(tbz(x7, 31, INST_OFF(0x4)), "tbz w7, #31, #+0x4"); in TEST_()
821 COMPARE_PREFIX(tbz(x8, 32, INST_OFF(0x8)), "tbz x8, #32, #+0x8"); in TEST_()
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| /external/bzip2/ |
| D | bzip2.txt | 56 filename.tbz becomes filename.tar
60 .bz2, .bz, .tbz2 or .tbz, bzip2 complains that it cannot
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| D | bzip2.1.preformatted | 59 filename.tbz becomes filename.tar
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| /external/v8/src/arm64/ |
| D | assembler-arm64.cc | 1039 void Assembler::tbz(const Register& rt, in tbz() function in v8::internal::Assembler
1048 void Assembler::tbz(const Register& rt, in tbz() function in v8::internal::Assembler
1052 tbz(rt, bit_pos, LinkAndGetInstructionOffsetTo(label)); in tbz()
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| D | assembler-arm64.h | 1071 void tbz(const Register& rt, unsigned bit_pos, Label* label);
1072 void tbz(const Register& rt, unsigned bit_pos, int imm14);
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| /external/vixl/src/vixl/a64/ |
| D | macro-assembler-a64.cc | 566 tbz(rt, bit_pos, &done); in Tbnz()
596 tbz(rt, bit_pos, label); in Tbz()
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| D | assembler-a64.h | 1201 void tbz(const Register& rt, unsigned bit_pos, Label* label);
1204 void tbz(const Register& rt, unsigned bit_pos, int imm14);
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| D | assembler-a64.cc | 809 void Assembler::tbz(const Register& rt, in tbz() function in vixl::Assembler
817 void Assembler::tbz(const Register& rt, in tbz() function in vixl::Assembler
820 tbz(rt, bit_pos, LinkAndGetInstructionOffsetTo(label)); in tbz()
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| /external/v8/src/ic/arm64/ |
| D | ic-arm64.cc | 1033 patcher.tbz(smi_reg, 0, branch_imm); in PatchInlinedSmiCode()
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| /external/vixl/test/ |
| D | test-disasm-a64.cc | 934 COMPARE_PREFIX(tbz(w4, 0, INST_OFF(0x7ffc)), "tbz w4, #0, #+0x7ffc"); in TEST()
935 COMPARE_PREFIX(tbz(x5, 63, INST_OFF(-0x8000)), "tbz x5, #63, #-0x8000"); in TEST()
936 COMPARE_PREFIX(tbz(w6, 31, INST_OFF(0)), "tbz w6, #31, #+0x0"); in TEST()
937 COMPARE_PREFIX(tbz(x7, 31, INST_OFF(0x4)), "tbz w7, #31, #+0x4"); in TEST()
938 COMPARE_PREFIX(tbz(x8, 32, INST_OFF(0x8)), "tbz x8, #32, #+0x8"); in TEST()
|