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Searched refs:uminv (Results 1 – 14 of 14) sorted by relevance

/external/llvm/test/CodeGen/AArch64/
Darm64-uminv.ll5 ; CHECK: uminv.8b b[[REG:[0-9]+]], v0
10 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a) nounwind
28 ; CHECK: uminv.4h h[[REG:[0-9]+]], v0
33 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %a) nounwind
49 ; CHECK: uminv.8h h[[REG:[0-9]+]], v0
54 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16> %a) nounwind
70 ; CHECK: uminv.16b b[[REG:[0-9]+]], v0
75 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %a) nounwind
91 ; CHECK: uminv.8b b[[REGNUM:[0-9]+]], v1
95 %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a2)
[all …]
Darm64-neon-across.ll21 declare i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32>)
23 declare i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16>)
25 declare i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8>)
33 declare i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16>)
35 declare i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8>)
273 ; CHECK: uminv b{{[0-9]+}}, {{v[0-9]+}}.8b
275 %uminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a)
276 %0 = trunc i32 %uminv.i to i8
282 ; CHECK: uminv h{{[0-9]+}}, {{v[0-9]+}}.4h
284 %uminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %a)
[all …]
Darm64-vecCmpBr.ll9 ; CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0
16 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %0) #3
34 ; CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0
42 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %0) #3
151 ; CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0
158 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %0) #3
174 ; CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0
181 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %0) #3
199 declare i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8>) #2
201 declare i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8>) #2
/external/llvm/test/MC/AArch64/
Dneon-across.s69 uminv b0, v1.8b
70 uminv b0, v1.16b
71 uminv h0, v1.4h
72 uminv h0, v1.8h
73 uminv s0, v1.4s
Dneon-diagnostics.s3776 uminv s0, v1.2s
3798 uminv d0, v1.2d define
/external/vixl/src/vixl/a64/
Dsimulator-a64.h2040 LogicVRegister uminv(VectorFormat vform,
Dmacro-assembler-a64.h2285 V(uminv, Uminv) \
Dassembler-a64.h3142 void uminv(const VRegister& vd,
Dsimulator-a64.cc2839 case NEON_UMINV: uminv(vf, rd, rn); break; in VisitNEONAcrossLanes()
Dlogic-a64.cc1593 LogicVRegister Simulator::uminv(VectorFormat vform, in uminv() function in vixl::Simulator
Dassembler-a64.cc4036 V(uminv, NEON_UMINV, true)
/external/vixl/test/
Dtest-simulator-a64.cc4035 DEFINE_TEST_NEON_ACROSS(uminv, Basic)
/external/vixl/doc/
Dsupported-instructions.md4184 void uminv(const VRegister& vd,
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td3830 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;